Reliability modeling of nanoelectronic circuits

2005 5th IEEE Conference on Nanotechnology

Volumn 1, Issue , 2005, Pages 269-272

  Han, Jie ^a   Taylor, Erin ^a   Gao, Jianbo ^a   Fortes, José ^a  

^a J Crayton Pruitt Family Department of Biomedical Engineering   (United States)

Author keywords

Fault tolerance; Nanoelectronics; Nanotechnology; Probabilistic; Reliability; Simulation

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; LOGIC GATES; NANOTECHNOLOGY; NETWORKS (CIRCUITS); PROBABILITY;

FUNDAMENTAL ERROR; NANOELECTRONIC CIRCUITS; PROBABILISTIC MODELS;

NANOSTRUCTURED MATERIALS;

EID: 33746970449     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. S.K. Shukla and R.I. Bahar, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, Kluwer Academic Publishers, 2004.
2. J. Han, Fault-Tolerant Architectures for Nanoelectronic and Quantum Devices, Ph.D. dissertation, Delft University of Technology, 2004. http://www.qi.tnw.tudelft.nl/~jie
3. J. Han and P. Jonker, "A defect- and fault-tolerant architecture for nanocomputers," Nanotechnology, vol. 14, no. 2, pp. 224-230, 2003.
4. R.I. Bahar, J. Chen and J. Mundy, "A probabilistic-based design for nanoscale computation," Chapter 5 in [1].
5. J.B. Gao, Y. Qi and J.A.B. Fortes, "Bifurcations and fundamental error bounds for fault-tolerant Computations," IEEE Tr. Nanotechnology, (in press).
6. S. Krishnaswamy, G.F. Viamontes, I.L. Markov and J.P. Hayes, "Accurate reliability evaluation and enhancement via probabilistic transfer matrices," DATE'05.
7. T. Oya, T. Asai, T. Fukui and Y. Amemiya, "A majority-logic device using an irreversible single-electron box," IEEE Tr. Nanotechnology, vol. 2, no. 1, pp. 15-22, 2003.
8. C.S. Lent and P.D. Tougaw, "A device architecture for computing with quantum dots," Proc. IEEE, vol. 85, pp. 541-557, 1997.
9. M.B. Tahoori, J. Huang, M. Momenzadeh and F. Lombardi, "Defects and faults in quantum cellular automata at nanoscale," 2004 IEEE VLSI Test Symp.
10. M. Sulieman and V. Beiu, "On single electron technology full adders," IEEE Nano 2004, pp.317-320, 2004.
11. R. Zhang, K. Walus, W. Wang and G.A. Jullien, "A method of majority logic reduction for quantum cellular automata," IEEE Tr. Nanotechnology, vol. 3, no. 4, pp. 443-450, 2004.
12. J. Han, E. Taylor, J. Gao and J. Fortes, "Faults, error bounds and reliability of nanoelectronic circuits," ASAP05.