Optimisation modelling for thermal fatigue reliability of lead-free interconnects in fine-pitch flip-chip packaging

Soldering and Surface Mount Technology

Volumn 21, Issue 1, 2009, Pages 11-24

  Stoyanov, Stoyan ^a   Bailey, Chris ^a   Desmulliez, Marc ^b  

^a UNIVERSITY OF GREENWICH   (United Kingdom)

^b HERIOT WATT UNIVERSITY   (United Kingdom)

Author keywords

Optimization; Product reliability; Prototypes; Techniques

Indexed keywords

ARCHITECTURAL DESIGN; BRAZING; CHIP SCALE PACKAGES; COPPER; DESIGN; ELECTRONIC EQUIPMENT MANUFACTURE; FLIP CHIP DEVICES; LEAD; NUMERICAL METHODS; OPTIMIZATION; PRODUCT DEVELOPMENT; PROJECT MANAGEMENT; QUALITY ASSURANCE; RELIABILITY; SOFTWARE RELIABILITY; THERMAL FATIGUE; WELDING;

COMPUTATIONAL APPROACHES; COMPUTATIONAL MODELLING; COPPER COLUMNS; DESIGN ENGINEERS; DESIGN METHODOLOGIES; DESIGN OPTIMISATION; DESIGN RULES; DESIGN STRATEGIES; DESIGN/METHODOLOGY/APPROACH; DEVELOPMENT STAGES; ELECTRONIC COMPONENTS; ELECTRONIC PACKAGES; FATIGUE RELIABILITIES; FINITE-ELEMENT ANALYSIS; FLIP CHIPS; FLIP-CHIP PACKAGES; FLIP-CHIP PACKAGING; INITIAL DESIGNS; INTERCONNECT LEVELS; LEAD-FREE; LEAD-FREE SOLDER JOINTS; NUMERICAL - TECHNIQUES; OPTIMAL DESIGNS; OPTIMISATION; POSITIVE EFFECTS; PRODUCT RELIABILITY; PROTOTYPES; PROTOTYPING PROCESS; SOFTWARE MODULES; SOLDER JOINTS; SOLDER MATERIALS; SOLDER WETTING; STATISTICAL ANALYSIS; TECHNIQUES; THERMO-MECHANICAL RELIABILITIES; VIRTUAL PROTOTYPING;

ELECTRONICS PACKAGING;

EID: 58849094565     PISSN: 09540911     EISSN: None     Source Type: Journal    
DOI: 10.1108/09540910910928265     Document Type: Article

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