Overview and future challenges of floating Body RAM (FBRAM) technology for 32nm technology node and beyond

ESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference

Volumn , Issue , 2008, Pages 25-29

  Hamamoto, Takeshi ^a   Ohsawa, Takashi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EXPERIMENTS; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE;

32 NM TECHNOLOGIES; EMBEDDED MEMORIES; FUTURE CHALLENGES; HIGH DENSITIES; MEMORY CELL DESIGNS; MEMORY CELLS; SINGLE CELLS; SOI SUBSTRATES;

BODIES OF REVOLUTION;

EID: 58049112663     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2008.4681692     Document Type: Conference Paper

References (9)

1. K.Inoh, et al., "FBC(Floating Body Cell) for Embedded DRAM on SOI," 2003 Symp. on VLSI Technology, pp.63-64.
2. T.Shino, et al., "Highly Scalable FBC(Floating Body Cell) with 25nm BOX Structure for Embedded DRAM Applications," 2004 Symp. on VLSI Technology, pp.132-133.
3. T.Shino, et al., "Fully-Depleted FBC(Floating Body Cell) with Enlarged Signal Window and Excellent Logic Process Compatibility," 2004 IEDM Tech. Dig., pp.281-284.
4. Y. Minami, et al, "A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology(CMOS4) for 128Mb SOI DRAM," 2005 IEDM, pp. 317-320.
5. T.Ohsawa, et al., "An 18.5ns 128Mb SOI DRAM with a Floating Body Cell," ISSCC Dig. Tech. Papers, pp.458-459, Feb, 2005.
6. T. Ohsawa, et al, "A 128Mb Floating Body RAM (FBRAM) on SOI with Multi-Averaging Scheme of Dummy Cell," 2006 Symp. on VLSI Circuits, pp.224-225.
7. T. Shino, et al, "Floating Body RAM Technology and its Scalability to 32nm Node and Beyond," 2006 IEDM Tech. Dig., pp. 569-572.
8. T. Hamamoto, et al., "A Floating-Body Cell Fully Compatible with 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and its Scalability," IEEE Trans. ED, 54(3), pp.563-571, 2007.
9. F. Matsuoka, et al., "FBC's potential of 6F2 Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin," 2007 IEDM Tech. Dig, pp.39-42.