Early models for system-level power estimation

Proceedings - International Workshop on Microprocessor Test and Verification

Volumn , Issue , 2007, Pages 8-14

  Woo, Dam Sun ^a   Al Sukhni, Hassan ^b   Holt, Jim ^b   Chiou, Derek ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; ELECTRIC POWER UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAMMABLE LOGIC CONTROLLERS; SPREADSHEETS; SYSTEM-ON-CHIP;

ARCHITECTURAL FEATURES; ARCHITECTURAL STRUCTURE; FPGA-BASED IMPLEMENTATION; FUNCTIONAL INFORMATION; INSTRUCTION COUNTS; POWER ESTIMATIONS; POWER SIMULATION; SYSTEM ON CHIP DESIGN;

INTEGRATED CIRCUIT DESIGN;

EID: 57849142472     PISSN: 15504093     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTV.2007.8     Document Type: Conference Paper

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