Microarchitectural power modeling techniques for deep sub-micron microprocessors

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 212-217

  Kim, Nam Sung ^a   Kgil, Taeho ^b   Bertacco, Valeria ^b   Austin, Todd ^b   Mudge, Trevor ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Deep sub micron; Power modeling

Indexed keywords

APPROXIMATION THEORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; NETWORKS (CIRCUITS); PARAMETER ESTIMATION; PERSONAL DIGITAL ASSISTANTS; SWITCHING; TABLE LOOKUP;

ARCHITECTURAL SIMULATION; DEEP SUB-MICRON; MICROARCHITECTURES; POWER MODELING;

MICROPROCESSOR CHIPS;

EID: 16244370396     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013290     Document Type: Conference Paper

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