Correction of operational amplifier gain error in pipelined A/D converters

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 1, Issue , 2001, Pages 568-571

  Ali, Ahmed M A ^a   Nagaraj, K ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

A/D CONVERTER; AMPLIFIER GAIN; DIGITAL DOMAIN; ERROR SIGNAL; FINITE GAIN; ORIGINAL SIGNAL; PIPELINED A/D CONVERTERS; TRANSISTOR-LEVEL SIMULATION;

OPERATIONAL AMPLIFIERS; ANALOG TO DIGITAL CONVERSION;

ELECTRIC DISTORTION; ERRORS; GAIN CONTROL; OPERATIONAL AMPLIFIERS; SIGNAL TO NOISE RATIO; TRANSISTORS;

PIPELINED AMPLIFIERS;

EID: 0034995986     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921919     Document Type: Conference Paper

References (7)

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3. th March, 2000. (Pubitemid 30587911)
4. K. Nagaraj, "Area-efficient self-calibration technique for pipe-lined algorithmic A/D converters", IEEE Trans. Circuits and Systems-Il, 43, pp. 540-544, July, 1996. (Pubitemid 126777597)
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6. H.-S. Lee, "A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC", IEEE J. Solid-State Circuits, 29, pp. 509-515, April, 1994.
7. P. C. Yu and H.-S. Lee, "A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement", IEEE J. Solid-State Circuits, 28, pp. 1265-1272, December, 1993.