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Volumn , Issue , 2008, Pages 112-115

A polynomial time approximation scheme for timing constrained minimum cost layer assignment

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED TECHNOLOGIES; CIRCUIT PERFORMANCES; COMPLETE PROBLEMS; GATE DELAYS; INTERCONNECT DELAYS; LAYER ASSIGNMENTS; METAL LAYERS; MINIMUM COSTS; NANOSCALE REGIMES; NEW ALGORITHMS; NEW DIMENSIONS; NUMBER OF NODES; OPTIMAL DYNAMICS; OPTIMAL LAYERS; POLYNOMIAL TIME APPROXIMATION SCHEMES; ROUTING LAYERS; THIN METALS; TIMING CONSTRAINTS; VLSI TECHNOLOGIES; WIRE SIZINGS;

EID: 57849083934     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681560     Document Type: Conference Paper
Times cited : (14)

References (15)
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  • 3
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  • 4
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    • Cong, J.1    Leung, K.-S.2    Zhou, D.3
  • 7
    • 0030110490 scopus 로고    scopus 로고
    • Optimal wire sizing and buffer insertion for low power and a generalized delay model
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  • 9
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    • Approximation, schemes for the restricted shortest path problem
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    • Hassin, R.1
  • 11
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    • S. Hu, C. J. Alpert, J. Hu, S. Karandikar, Z. Li, W. Shi, and C. N. Sze, Fast algorithms for slew constrained minimum cost buffering, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 26, no. 11, pp. 2009-2022, 2007.
    • S. Hu, C. J. Alpert, J. Hu, S. Karandikar, Z." Li, W. Shi, and C. N. Sze, "Fast algorithms for slew constrained minimum cost buffering," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 2009-2022, 2007.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.