Nano-electro-mechanical nonvolatile memory (NEMory) cell design and scaling

IEEE Transactions on Electron Devices

Volumn 55, Issue 12, 2008, Pages 3482-3488

  Choi, Woo Young ^a   Osabe, Taro ^b   King Liu, Tsu Jae ^c  

^a Sogang University   (South Korea)

^b HITACHI LTD   (Japan)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Cell design; Finite element analysis (FEA); Nano electro mechanical nonvolatile memory (NEMory); Scaling

Indexed keywords

ALUMINA; DATA STORAGE EQUIPMENT; SCALABILITY;

ANALYTICAL MODELING; CELL DESIGN; CELL DESIGNS; CELL DIMENSIONS; FEA SIMULATIONS; FINITE ELEMENT ANALYSIS; FINITE ELEMENT ANALYSIS (FEA); FRACTURE STRAINS; FUNDAMENTAL LIMITS; GAP THICKNESSES; LENGTH SCALING; LOW OPERATING VOLTAGES; LOW VOLTAGES; LOW YOUNG'S MODULUS; MECHANICAL MEMORIES; NANO-ELECTRO-MECHANICAL NONVOLATILE MEMORY (NEMORY); NONVOLATILE MEMORIES; PROGRAM/ERASE; SCALING; STORAGE DENSITIES;

FINITE ELEMENT METHOD;

EID: 57149125169     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2006540     Document Type: Article

References (14)

1. C.-G. Hwang, "Nanotechnology enables a new memory growth model," Proc. IEEE, vol. 91, no. 91, pp. 1765-1771, Nov. 2003.
2. D. Gogl, C. Arndt, J. C. Barwin, A. Bette, J. DeBrosse, E. Gow, H. Hoenigschmid, S. Lammers, M. Lamorey, L. Yu, T. Maffitt, K. Maloney, W. Obermaier, A. Sturm, H. Viehmann, D. Willmott, M. Wood, W. J. Gallagher, G. Mueller, and A. R. Sitaram, "A 16-Mb MRAM featuring bootstrapped write drivers," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 902-908, Apr. 2005.
3. S. L. Cho, J.H. Yi, Y. H. Ha, B. J. Kuh, C. M. Lee, J. H. Park, S. D. Nam, H. Horii, B. K. Cho, K. C. Ryoo, S. O. Park, H. S. Kim, U.-I. Chung, J. T. Moon, and B. I. Ryu, "Highly scalable on-axis confined cell structure for high density PRAM beyond 256 Mb,"in VLSI Symp. Tech. Dig., Jun. 2005, pp. 96-97.
4. M. Despont, U. Drechsler, R. Yu, H. B. Pogge, and P. Vettiger, "Wafer-scale microdevice transfer/interconnect: Its application in an AFM-based data-storage system," J. Microelectromech. Syst., vol. 13, no. 6, pp. 895-901, Dec. 2004.
5. W. Y. Choi, H. Kam, D. Lee, J. Lai, and T.-J. King Liu, "Compact nano-electro-mechanical non-volatile memory (NEMory) for 3D integration," in IEDM Tech. Dig., Dec. 2007, pp. 603-606.
6. J. T. Watt, B. J. Fishbein, and J. D. Plummer, "A low-temperature NMOS technology with Cesium-implanted load devices," IEEE Trans. Electron Devices, vol. ED-34, no. 1, pp. 28-38, Jan. 1987.
7. W. W. Jang, J. O. Lee, J.-B. Yoon, M.-S. Kim, J.-M. Lee, S.-M. Kim, K.-H. Cho, D.-W. Kim, D. Park, and W.-S. Lee, "Fabrication and characterization of a nanoelectromechanical switch with 15-nm-thick suspension air gap," Appl. Phys. Lett., vol. 92, no. 10, p. 103 110, Mar. 2008.
8. ANSYS, 2005, ANSYS Inc. Release 10.0.
9. P. M. Osterberg and S. D. Senturia, "M-TEST: A test chip for MEMS material property measurement using electrostatically actuated test structures," J. Microelectromech. Syst., vol. 6, no. 2, pp. 107-118, Jun. 1997.
10. G. M. Rebeiz, RF MEMS Theory, Design, and Technology. Hoboken, NJ: Wiley, 2003.
11. M. H. White, D. A. Adams, and J. Bu, "On the go with SONOS," IEEE Circuits Devices Mag., vol. 16, no. 4, pp. 22-31, Jul. 2000.
12. MATLAB, 2002, MathWorks Inc. Release 13.
13. T. Rafael, "The London-van der Waals interaction energy between objects of various geometries," J. Phys., Condens. Matter, vol. 13, no. 9, pp. L195-L202, Mar. 2001.
14. D. T. Lee, T. Osabe, and T.-J. King Liu, to be published.