Laser annealed junctions: Process integration sequence optimization for advanced CMOS technologies

Extended Abstracts of the 7th International Workshop on Junction Technology, IWJT 2007

Volumn , Issue , 2007, Pages 137-140

  Hoffmann, T ^a   Noda, T ^a   Felch, S ^b   Severi, S ^a   Parihar, V ^b   Forstner, H ^b   Vrancken, C ^a   De Potter, M ^a   Van Daele, B ^a   Bender, H ^a   Niwa, M ^a   Schreutelkamp, R ^b   Vandervorst, W ^a   Biesemans, S ^a   Absil, P P ^a  

^a IMEC   (Belgium)

^b APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

ABSORBING LAYERS; ANNEALING SEQUENCE; NON-MELT LASER ANNEALING; POLY-DEPLETION; PROCESS INTEGRATION; SEQUENCE OPTIMIZATION; SHORT-CHANNEL EFFECT; TRANSISTOR PERFORMANCE;

ANNEALING;

EID: 47649113938     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWJT.2007.4279968     Document Type: Conference Paper

References (10)

1. A. Shima, et al., in Symp. VLSI Tech. Dig., p. 174 (2004).
2. K. Adachi, et al., in Symp. VLSI Tech. Dig., p. 142 (2005).
3. S. Fung, et al., in Symp. VLSI Tech. Dig., p. 92 (2004).
4. Severi, et al., IEDM2006, p. 859 (2006).
5. B. Josse, et al., IEDM2006, p.693 (2006).
6. T. Noda, et al., IEDM2006, p. 377 (2006).
7. T. Feudel et al., RTP Conference (2006).
8. M. Jaraiz, et al., Mat. Res. Soc. Symp. Proc. 532, 43 (1998).
9. N. Cagnat et al., Mat. Res. Soc. Symp. Proc. (2006).
10. C. Nieh, et al., IEEE EDL. 27, p. 969 (2006).