Process integration issues with spike, flash and laser anneal implementation for 90 and 65 nm technologies

14th IEEE International Conference on Advanced Thermal Processing of Semiconductors, RTP 2006

Volumn , Issue , 2006, Pages 73-78

  Feudel, Th ^a   Horstmann, M ^a   Herrmann, L ^a   Herden, M ^a   Gerhardt, M ^a   Greenlaw, D ^a   Fisher, P ^b   Kluth, J ^b  

^a IBM MICROELECTRONICS   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

65NM TECHNOLOGIES; ACTIVE AREAS; FLASH ANNEAL; GATE OXIDES; LASER ANNEAL; LATERAL DEVICES; LOGIC TECHNOLOGIES; NEW MATERIALS; PATTERN EFFECTS; PERFORMANCE ENHANCEMENTS; POLY DEPLETIONS; POWER DENSITIES; PROCESS INTEGRATIONS; TRANSISTOR PARAMETERS; TRANSISTOR SCALING; WITH OR WITHOUT;

CRYSTALS; ELECTRIC CONDUCTIVITY; INTERNET PROTOCOLS; RAPID THERMAL ANNEALING; RAPID THERMAL PROCESSING; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR LASERS; SEMICONDUCTOR MATERIALS;

TRANSISTORS;

EID: 33846201143     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTP.2006.367984     Document Type: Conference Paper

References (8)

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3. C.-H. Chen et al., Channel stress modulation and pattern loading effect minimization of milli-scond super anneal for sub-65nm high performance SiGe CMOS, Symp. VLSI Tech., 2006.
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5. I.Ahsan et al., RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology, Symp. VLSI Tech., 2006.
6. K.Adachi et al., Issues and optimization of millisecond anneal process for 45nm node and beyond, Symp. VLSI Tech., 2005, p. 142
7. Th.Feudel et al., Junction scaling for next generation microprocessor technologies, Tech.Symp. Semicon Europe, Munich, April 2005.
8. T. Yamashita et al., High Performance 65nm SOI Transistors Using Laser Spike Annealing, Proc. European Solid-State Device Research Conference (ESSDERC) 2006.