High-activation laser anneal process for the 45nm CMOS technology platform

15th IEEE International Conference on Advanced Thermal Processing of Semiconductors, RTP 2007

Volumn , Issue , 2007, Pages 251-256

  Bidaud, M ^a   Bono, H ^b   Chaton, C ^b   Dumont, B ^a   Huard, V ^a   Morin, P ^a   Proencamota, L ^a   Ranica, R ^a   Ribes, G ^a  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG DIFFERENTIAL ANALYZERS; ANNEALING; CMOS INTEGRATED CIRCUITS; CRYSTALS; ELECTRIC CONDUCTIVITY; INTERNET PROTOCOLS; LASERS; PLASMA DEPOSITION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; RAPID THERMAL ANNEALING; RAPID THERMAL PROCESSING; SEMICONDUCTOR JUNCTIONS; SEMICONDUCTOR LASERS; SEMICONDUCTOR MATERIALS;

ABSORBING FILMS; ABSORBING LAYERS; CMOS TECHNOLOGIES; DAMAGE-FREE; DEFECTIVITY; DRIVE CURRENTS; DYNAMIC SURFACES; GATE OXIDE INTEGRITIES; INTEGRATION SCHEMES; JUNCTION LEAKAGES; LASER ANNEAL; LASER ANNEALING; LASER TECHNIQUES; LOW TEMPERATURES; MANUFACTURABILITY; MICROSCOPIC UNIFORMITIES; PROCESS SIMPLICITIES; PROCESS WINDOWS; SHORT CHANNELS; SOLUBILITY LIMITS; SOURCE/DRAIN JUNCTIONS; SURFACE EMISSIVITIES; TRANSISTOR RELIABILITIES; WAFER STRESSES;

TRANSISTORS;

EID: 47949128100     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTP.2007.4383850     Document Type: Conference Paper

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