A 430 MHz, 280 mW processor for the conversion of cartesian to polar coordinates in 0.25 μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 11, 2008, Pages 2503-2513

  Strollo, Antonio Giuseppe Maria ^a   De Caro, Davide ^a   Petra, Nicola ^a  

^a UNIVERSITY OF NAPLES FEDERICO II   (Italy)

Author keywords

Application specific integrated circuits (ASICs); CMOS integrated circuits; Coordinate conversions; Digital communications; Double pass transistor (DFL); Full adder; Low power CMOS design

Indexed keywords

APPLICATION-SPECIFIC INTEGRATED CIRCUITS (ASICS); COORDINATE CONVERSIONS; DIGITAL COMMUNICATIONS; DOUBLE-PASS TRANSISTOR (DFL); FULL-ADDER; LOW-POWER CMOS DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; DIGITAL CIRCUITS; DIGITAL COMMUNICATION SYSTEMS; DIGITAL INTEGRATED CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUITS; MOS CAPACITORS; NETWORKS (CIRCUITS); NUMBER THEORY; TABLE LOOKUP;

CMOS INTEGRATED CIRCUITS;

EID: 56849124676     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2005816     Document Type: Article

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