Generating physical addresses directly for saving instruction TLB energy

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 185-196

  Kadayif, I ^a   Sivasubramaniam, A ^a   Kandemir, M ^a   Kandiraju, G ^a   Chen, G ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Batteries; Clocks; Cooling; Energy consumption; Fabrication; Frequency; Optimization; Packaging; Power dissipation; Thermal management

Indexed keywords

BUFFER STORAGE; CLOCKS; COMPUTER ARCHITECTURE; COOLING; ENERGY DISSIPATION; ENERGY UTILIZATION; FABRICATION; OPTIMIZATION; PACKAGING; SOLAR CELLS; TEMPERATURE CONTROL;

CACHE DESIGN; DYNAMIC POWER; FREQUENCY; INSTRUCTION CACHES; PERFORMANCE OPTIMIZATIONS; POWER DENSITIES; POWER SAVINGS; TRANSLATION LOOKASIDE BUFFER;

PHYSICAL ADDRESSES;

EID: 84906809658     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2002.1176249     Document Type: Conference Paper

References (29)

1. A. Ailamaki, D. J. DeWitt, M. D. Hill, and D. A. Wood. DBMSs on a modern processor: where does time go?. In Proc. 25th International Conference on Very Large Data Bases, Edinburgh, UK, September 1999.
2. R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory hierarchy reconýguration for energy and performance in general-purpose processor architectures. In Proc. 33rd International Symposium on Microarchitecture, pp. 245-257, December 2000.
3. P. Bose et al. Early-stage deýnition of LPX: A low power issueexecute processor prototype. In Proc. 2nd Workshop on Power-Aware Computer Systems (in conjunction with HPCA'02), Cambridge, MA, February 2, 2002.
4. D. Brooks and M. Martonosi. Dynamic thermal management for high-performance microprocessors. In Proc. International Symposium on High-Performance Computer Architecture, January, 2001.
5. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. 27th International Symposium on Computer Architecture, Vancouver, British Columbia, June 2000.
6. D. Burger, T. Austin, and S. Bennett. Evaluating future microprocessors: the SimpleScalar tool set. Technical Report CS-TR-96-103, Computer Science Department, University of Wisconsin, Madison, July 1996.
7. F. Catthoor, S. Wuytack, E. D. Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle. Custom Memory Management Methodology-Exploration of Memory Organization for Embedded Multimedia System Design. Kluwer Academic Publishers, 1998.
8. M. Cekleov, and M. Dubois. Virtual-address caches. Part 1: Problems and solutions in uniprocessors. IEEE Micro, 17(5):64-71, SeptemberñOctober, 1997.
9. T-C. Chiueh and R. H. Katz. Eliminating the Address Translation Bottleneck for Physical Address Cache. In Proc. ASPLOS, pages 137-148, 1992.
10. J-H. Choi, J-H. Lee, S-W. Jeong, S-D. Kim, and C. Weems. A low-power TLB structure for embedded systems. IEEE Computer Architecture Letters, Volume 1, January 2002.
11. D. Folegnani and A. Gonzalez. Energy-effective issue logic. In Proc. 28th International Symposium on Computer Architecture, Goteborg, Sweeden, June 30ñJuly 4, 2001.
12. K. Ghose and M. B. Kamble. Reducing power in superscalar processor caches using subbanking, multiple line buffers, and bit-line segmentation. In Proc. 1999 International Symposium Low Power Electronics and Design, 1999, pages 70-75.
13. J. L. Henning. SPEC2000: Measuring CPU performance in the new millenium, IEEE Computer Magazine, July 2000, pp. 28-35.
14. K. Inoue, T. Ishihara, and K. Murakami. Way-predicting setassociative cache for high performance and low energy consumption. In Proc. International Symposium on Low Power Electronics and Design, pages 273-275, 1999.
15. Intel StrongARM Processor. http://www. intel. com /design/pca/applicationsprocessors/1110 brf. htm
16. Itanium Manual. http://developer. intel. com/ design/itanium/manuals. htm.
17. B. Jacob and T. Mudge. Uniprocessor virtual memory without TLBs. IEEE Transactions on Computers, vol. 50, no. 5, pp. 482-499. May 2001.
18. T. Juan, T. Lang, and J. J. Navarro. Reducing TLB power requirements. In Proc. International Symposium on Low Power Electronics and Design, 1997.
19. I. Kadayif, A. Sivasubramaniam, M. Kandemir, G. Kandiraju, and G. Chen. Generating physical addresses directly for saving instruction TLB energy. Technical Report CSE-TR-02-012, Department of Computer Science and Engineering, Pennsylvania State university, June 2002.
20. S. Kim. Low power MMU design for embedded processors. http://supercom. yonsei. ac. kr/temp/sam. ppt
21. J. Knight, and P. Rosenfeld. Segmented virtual to real translation assist. IBM Technical Disclosure Bulletin, 27(2):1077-1078, July 1984.
22. R. Maddock, B. Marks, J. Minshull and M. Pinnell. Hardware address relocation for variable length segments. IBM Technical Disclosure Bulletin, 23(11):5186-5187, April 1981.
23. D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan. Power issues related to branch prediction. In Proc. Eighth International Symposium on High-Performance Computer Architecture, pp. 233-244, February 2002.
24. G. Reinman and N. P. Jouppi. CACTI 2. 0: An integrated cache timing and power model. Compaq, WRL, Research Report 2000/7, February 2000.
25. D. Sima, T. Fountain, and P. Kacsuk. Advanced Computer Architecture: A Design Space Approach, Addison-Wesley, 1997.
26. W. D. Strecker. VAX-11/780: A virtual address extension to the DEC PDP-11 family. In Proc AFIPS NCC, vol. 47, pp. 967-980, 1978.
27. N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. Y. Kim, and W. Ye. Energy-driven integrated hardware-software optimizations using SimplePower. In Proc. International Symposium on Computer Architecture, June 2000.
28. J. Yang, Y. Zhang, and R. Gupta. Frequent value compression in data caches. In Proc. 33rd International Symposium on Microarchitecture, pages 258-265, Monterey, CA, December 2000.
29. V. Zyuban and P. Kogge. Split register ýle architectures for inherently lower power microprocessors. In Proc. Power-Driven Microarchitecture Workshop (in conjunction with ISCA'98), pages 32-37, 1998.