10-Gb/s inductorless CDRs with digital frequency calibration

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 9, 2008, Pages 2514-2524

  Liang, Che Fu ^a   Chu, Hong Lin ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Clock and data recovery; Digital frequency calibration; Gated oscillator; Inductorless

Indexed keywords

CALIBRATION; CLOCKS; ELECTRIC INDUCTORS; ELECTRIC POWER UTILIZATION; JITTER; OSCILLATORS (ELECTRONIC);

CLOCK AND DATA RECOVERY; CMOS PROCESSS; DIGITAL CONTROLLED OSCILLATORS; DIGITAL FREQUENCY CALIBRATION; GATED OSCILLATORS; GATING TECHNIQUES; INDUCTORLESS; PEAK-TO-PEAK JITTER;

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS);

EID: 56349171388     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.920096     Document Type: Article

References (13)

1. G.984.2 Gigabit-Capable Passive Optical Networks (GPON): Physical Media Dependent (PMD) Layer ITU-T, 2003.
2. M. Banu and A. E. Dunlop, "A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig., Feb. 1993, pp. 102-103.
3. A. E. Dunlop, W. C. Fischer, M. Banu, and T. Gabara, "150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig., Feb. 1995, pp. 44-45.
4. Y. Ota, R. G. Swartz, M. Banu, and A. E. Dunlop, "High-speed, burst-mode, packet-capable optical receiver and instantaneous clock recovery for optical bus operation," J. Lightw. Technol., vol. 12, no. 2, pp. 325-331, Feb. 1994.
5. J. Hwang, C. Park, and C. Park, "155-Mb/s burst-mode clock recovery circuit using the jitter reduction technique," IEICE Trans. Commun. vol. E86-B, no. 4, pp. 1423-1426, Apr. 2003.
6. Y. G. Kim, C. O. Lee, S. W. Lee, H. S. Chai, H. S. Ryu, and W. Y. Choi, "Novel 622 Mb/s burst-mode clock and data recovery circuits with muxed oscillators," IEICE Trans. Commun., vol. E86-B, pp. 3288-3292, Nov. 2003.
7. P. Han and W. Y. Choi, "1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-μm CMOS," in IEEE Int. Symp. Circuits Syst. (ISCAS), May 2006, pp. 3069-3072.
8. S. Kaeriyama et al., "A 10 Gb/s/ch 50 mW 120 × 130 μm2 clock and data recovery circuit," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig., Feb. 2003, pp. 70-71.
9. M. Nogawa, K. Nishimura, S. Kimura, T. Yoshida, T. Kawamura, M. Togashi, K. Kumozaki, and Y. Ohtomo, "A 10 Gb/s burst-mode CDR IC in 0.13 μm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig., Feb. 2005, pp. 228-229.
10. C. F. Liang, S. C. Hwu, and S. I. Liu, "A 10 Gb/s burst-mode CDR in 0.18 μm CMOS," in Proc. IEEE Custom Integr. Circuits Conf. (CICC) Sep. 2006, pp. 599-602.
11. A. Rossi and G. Fucilli, "Nonredundant successive approximation register for A/D converters," Electron. Lett., vol. 32, no. 12, pp. 1055-1057, Jun. 1996.
12. J. Savoj and B. Razavi, "A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector," IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 13-21, Jan. 2003.
13. S. Byun, J. C. Lee, J. H. Shim, K. Kim, and H. K. Yu, "A 10-Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2566-2576, Nov. 2006.