1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18-μm CMOS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3069-3072

  Han, Pyung Su ^a   Choi, Woo Young ^a  

^a Yonsei University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CLOCKS;

BURST-MODE CLOCK RECOVERY CIRCUIT; DATA EDGES; DUAL BIT-RATE STRUCTURE;

CMOS INTEGRATED CIRCUITS;

EID: 34247139985     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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9. Do-ho Kim, Pyung-Su Han, and Woo-Young Choi, "1.25Gb/s burst-mode CDR with robustness to duty cycle distortion", SOC conference 2005