Novel 622 Mb/s burst-mode clock and data recovery circuits with muxed oscillators

IEICE Transactions on Communications

Volumn E86-B, Issue 11, 2003, Pages 3288-3292

  Kim, Yu Gun ^a   Lee, Chun Oh ^a   Lee, Seung Woo ^a   Chai, Hyun Su ^b   Ryu, Hyun Suk ^b   Choi, Woo Young ^a  

^a Yonsei University   (South Korea)

^b Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

Burst mode; CDR; PLL; PON

Indexed keywords

OPTICAL COMMUNICATION; OPTIMAL SYSTEMS; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

BURST MODE CLOCK CIRCUITS; DATA RECOVERY CIRCUITS; PASSIVE OPTICAL NETWORKS;

DATA COMMUNICATION SYSTEMS;

EID: 0344309037     PISSN: 09168516     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Letter

References (4)

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3. M. Banu and A.E. Dunlop, "Clock recovery circuits with instantaneous locking," Electron. Lett., vol.28, no.23, pp.2127-2130, 1992.
4. A.E. Dunlop, W.C. Fischer, M. Banu, and T. Gabara, "150/30 Mb/s CMOS non-oversampled," Proc. 1995 IEEE International Solid State Circuit Conferences, pp.44-46, 1995.