-
1
-
-
0036923438
-
FinFET scaling to 10 nm gate length
-
B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. J. King, J. Bokor, C. Hu, M. R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, pp. 251-254.
-
(2002)
IEDM Tech. Dig
, pp. 251-254
-
-
Yu, B.1
Chang, L.2
Ahmed, S.3
Wang, H.4
Bell, S.5
Yang, C.6
Tabery, C.7
Ho, C.8
Xiang, Q.9
King, T.J.10
Bokor, J.11
Hu, C.12
Lin, M.R.13
Kyser, D.14
-
2
-
-
0029406037
-
Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits
-
Nov
-
M. Chan, B. Yu, Z. J. Ma, C. T. Nguyen, C. Hu, and P. K. Ko, "Comparative study of fully depleted and body-grounded non fully depleted SOI MOSFETs for high performance analog and mixed signal circuits," IEEE Trans. Electron Devices, vol. 42, no. 11, pp. 1975-1981, Nov. 1995.
-
(1995)
IEEE Trans. Electron Devices
, vol.42
, Issue.11
, pp. 1975-1981
-
-
Chan, M.1
Yu, B.2
Ma, Z.J.3
Nguyen, C.T.4
Hu, C.5
Ko, P.K.6
-
3
-
-
0031341418
-
Floating body effects in polysilicon thin-film transistors
-
Dec
-
M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I. Policicchio, "Floating body effects in polysilicon thin-film transistors," IEEE Trans. Electron Devices, vol. 44, no. 12, pp. 2234-2241, Dec. 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, Issue.12
, pp. 2234-2241
-
-
Valdinoci, M.1
Colalongo, L.2
Baccarani, G.3
Fortunato, G.4
Pecora, A.5
Policicchio, I.6
-
4
-
-
0030410185
-
Deep salicidation using nickel for suppressing the floating body effect in partially depleted SOI-MOSFET
-
Sanibal island, FL
-
F. Deng, R. A. Johnson, W. B. Dubbeldav, G. A. Garcia, P. M. Asbeck, and S. S. Lau, "Deep salicidation using nickel for suppressing the floating body effect in partially depleted SOI-MOSFET," in Proc. IEEE Int. SOI Conf., Sanibal island, FL, 1996, pp. 78-79.
-
(1996)
Proc. IEEE Int. SOI Conf
, pp. 78-79
-
-
Deng, F.1
Johnson, R.A.2
Dubbeldav, W.B.3
Garcia, G.A.4
Asbeck, P.M.5
Lau, S.S.6
-
5
-
-
0037004519
-
Fully-depleted SOI CMOSFETs with the fully-silicided source/dram structure
-
Dec
-
T. Ichimori and N. Hirashita, "Fully-depleted SOI CMOSFETs with the fully-silicided source/dram structure," IEEE Trans. Electron Devices vol. 49, no. 12, pp. 2296-2300, Dec. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.12
, pp. 2296-2300
-
-
Ichimori, T.1
Hirashita, N.2
-
6
-
-
29044440093
-
FinFET - A self-sligned douhle-gate MOSFET scalable to 20 nm
-
Dec
-
D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, "FinFET - A self-sligned douhle-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.C.2
Kedzierski, J.3
Takeuchi, H.4
Asano, K.5
Kuo, C.6
Anderson, E.7
King, T.J.8
Bokor, J.9
Hu, C.10
-
7
-
-
0033352172
-
Effects of plassma treatments, substrate types, and crystallization methods on performance and reliability of low temperatnre, polysilicon TFTs
-
C. W. Lin, M. Z. Yang, C. C. Yeh, L. J. Cheng, T. Y. Huang, H. C. Cheng, H. C. Lin, T. S. Chao, and C. Y Chang, "Effects of plassma treatments, substrate types, and crystallization methods on performance and reliability of low temperatnre, polysilicon TFTs," in IEDM Tech. Dig., 1999, pp. 305-308.
-
(1999)
IEDM Tech. Dig
, pp. 305-308
-
-
Lin, C.W.1
Yang, M.Z.2
Yeh, C.C.3
Cheng, L.J.4
Huang, T.Y.5
Cheng, H.C.6
Lin, H.C.7
Chao, T.S.8
Chang, C.Y.9
-
8
-
-
33645638134
-
High-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate, structure
-
Apr
-
P. Y. Kuo, T. S. Chao, R. J. Wang, and T. F. Lei, "High-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate, structure," IEEE Electron Device Lett., vol. 27, no. 4, pp. 258-261, Apr. 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.4
, pp. 258-261
-
-
Kuo, P.Y.1
Chao, T.S.2
Wang, R.J.3
Lei, T.F.4
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