Fully-depleted SOI CMOSFETs with the fully-silicided source/drain structure

IEEE Transactions on Electron Devices

Volumn 49, Issue 12, 2002, Pages 2296-2300

  Ichimori, Takashi ^a   Hirashita, Norio ^a  

^a OKI ELECTRIC INDUSTRY CO   (Japan)

Author keywords

Bipolar junction transistor; CHEPSA Co salicide; Cobalt silicide; Contact resistivity; Floating body effect; Parasitic resistance; Single facet interface

Indexed keywords

BIPOLAR TRANSISTORS; COBALT COMPOUNDS; ELECTRIC CONDUCTIVITY; ELECTRIC RESISTANCE; HETEROJUNCTIONS; INTERFACES (MATERIALS); ION IMPLANTATION; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

BIPOLAR JUNCTION TRANSISTOR; COBALT SILICIDE; CONTACT RESISTIVITY; FLOATING BODY EFFECT; PARASITIC RESISTANCE; SILICON ON INSULATOR CMOSFETS; SINGLE-FACET INTERFACE;

MOSFET DEVICES;

EID: 0037004519     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.807443     Document Type: Article

References (20)

1. J. P. Colinge, "SOI technology for deep submicron CMOS application," in Proc. 4th Int. Symp. Ultra Large Scale Integration Science and Technology, Electrochem Soc., vol. 93, Honolulu, HI, pp. 39-54.
2. T. Tsuchiya, T. Ohno, and Y. Kado, "Present status and potential of subquarter-Micron ultra-thin-film CMOS/SIMOX technology," in Proc. 6th Int. Symp. SOI Technology and Devices, Electrochem. Soc., vol. 94, 1994, pp. 401-412.
3. Y. Yamaguchi, T. Nishimura, Y. Akasaka, and K. Fujibayashi "Self-aligned silicide technology for ultra-thin SIMOX MOSFETs," IEEE Trans. Electron Devices, vol. 39, pp. 1179-1183, May 1992.
4. L. T. Su, M. J. Sherony, H. Hu, J. E. Chung, and D. A. Antoniadis, "Optimization of series resistance in sub-0.2 μm SOI MOSFETs," in IEDM Tech. Dig., 1993, pp. 723-726.
5. ____, "Optimization of series resistance in sub-0.2 μm SOI MOSFETs," IEEE Electron Device Lett., vol. 15, pp. 363-365, Sept. 1994.
6. J. Foerstner, J. Jones, M. Huang, B.-Y. Hwang, M. Racanelli, J. Tsao, and N. D. Theodore, "Behavior of contact-silicided TFSOI gate-structure," in Proc. 1993 IEEE Int. SOI Conf., 1993, pp. 86-87.
7. T. Nakamura, H. Matsuhashi, Y. Katakura, and J. Kanamori, "Optimization of selective epitaxy process for elevated source/drain applicable to 0.15 μm fully depleted CMOS on 25 nm SOI," in Ext. Abst. 2000 Int. Conf. Solid State Devices and Materials, 2000, pp. 476-477.
8. M. Takahashi, T. Ohno, Y. Sakakibara, and K. Takayama, "Fully depleted 20-nm SOI CMOSFETs with W-clad gate/source/drain layers," IEEE Trans. Electron Devices, vol. 48, pp. 1380-1385, July 2001.
9. T. Ichimori, N. Hirashita, and J. Kanamori, "Advanced Co salicide technology for sub-0.2μm FD-SOI devices," in Ext. Abst. 2000 Int. Conf. Solid State Devices and Materials, 2000, pp. 478-479.
10. T. Ichimori and N. Hirashita, "Advanced Co salicide technology for sub-0.2μm FD-SOI devices," Jpn. J. Appl. Phys., vol. 40, no. 4B, pp. 2881-2885, 2001.
11. ____,"Co salicide technology for sub-0.15μm FD-SOI and beyond: Super-flat silicide and fully-silicided source/drain structure," in Proc. 2000 IEEE Int. SOI Conf., 2000, pp. 72-73.
12. T. Ohno, M. Takashi, A. Ohtaka, Y. Sakakibara, and T. Tsuchiya, "Suppression of the parasitic bipolar effect in ultra-thin-film nMOSFETs/SIMOX by Ar Ion implantation into source/drain regions," in IEDM Tech. Dig., 1995, pp. 627-630.
13. 2/Si interface incorporated in a silicon-on-insulator metal-oxide-semiconductor-field-effect-transistor," Jpn. J. Appl. Phys., vol. 40, no. 10A, pp. L1019-L1021, 2001.
14. F. Deng, R. A. Johnson, W. B. Dubbelday, G. A. Garcia, P. M. Asbeck, and S. S. Lau, "Deep salicidation using nickel for suppressing the floating body effect in partially depleted SOI-MOSFET," in Proc. 1997 IEEE Int. SOI Conf., 1997, pp. 78-79.
15. S. P. Sinha, A. Zaleski, and D. E. Ioannou, "Investigation of carrier generation in fully depleted enhancement and accumulation mode SOI MOSFETs," IEEE Trans. Electron Devices, vol. 41, pp. 2413-2416, Dec. 1994.
16. J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, "A new method to determine MOSFET channel length," IEEE Electron Device Lett., vol. EDL-1, pp. 170-173, Sept. 1980.
17. C. M. Osburn and K. R. Bellur, "Low parasitic resistance contacts for scaled ULSI devices," Thin Solid Films, vol. 332-428-436, 1998.
18. K. K. Ng and R. Liu, "On the calculation of specific contact resistivity on <100> Si," IEEE Trans. Electron Devices, vol. 37, pp. 1535-1537, June 1990.
19. K. Varahramyan and E. J. Verret, "A model for specific contact resistance applicable for titanium silicide-silicon contacts," Solid-State Electron., vol. 39, no. 11, pp. 1601-1607, 1996.
20. D. B. Scott, R. A. Chapman, C.-C. Wei, S. S. Mahant-Shetti, R. A. Haken, and T. C. Holloway, "Titanium disilicide contact resistivity and its impact on 1-μm CMOS circuit performance," IEEE Trans. Electron Devices, vol. ED-34, pp. 562-574, Mar. 1987.