Work-function engineering for 32-nm-node pMOS devices: High-performance TaCNO-gated films

IEEE Electron Device Letters

Volumn 29, Issue 11, 2008, Pages 1203-1205

  O'Sullivan, Barry J ^a   Mitsuhashi, Riichirou ^a,b   Ito, Satoru ^a,b   Oikawa, Kota ^a,b   Kubicek, Stefan ^a   Paraschiv, Vasile ^a   Adelmann, Christoph ^a   Veloso, Anabela ^a   Yu, Hong ^a,c   Schram, Tom ^a   Biesemans, Serge ^a   Nakabayashi, T ^b   Ikeda, Atsushi ^b   Niwa, Masaaki ^a,b  

^a IMEC   (Belgium)

^b PANASONIC CORPORATION   (Japan)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

High ; PFET; TaCNO; Work function engineering

Indexed keywords

DIELECTRIC MATERIALS; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; MESFET DEVICES; PROBABILITY DENSITY FUNCTION; SILICON COMPOUNDS;

EFFECTIVE WORK FUNCTIONS; EQUIVALENT OXIDE THICKNESSES; INTERFACE LAYERS; METAL GATES; PFET; PMOS DEVICES; TACNO; TRANSISTOR CHARACTERISTICS; WORK-FUNCTION ENGINEERING;

FIELD EFFECT TRANSISTORS;

EID: 55249122290     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2005214     Document Type: Article

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