Estimation of fixed charge densities in hafnium-silicate gate dielectrics

IEEE Transactions on Electron Devices

Volumn 53, Issue 10, 2006, Pages 2627-2633

  Kaushik, Vidya S ^a   O'Sullivan, Barry J ^a,b   Pourtois, Geoffrey ^a   Van Hoornick, Nausikaä ^a   Delabie, Annelies ^a   Van Elshocht, Sven ^a   Deweerd, Wim ^a,c   Schram, Tom ^a   Pantisano, Luigi ^a   Rohr, Erika ^a   Ragnarsson, Lars Åke ^a   De Gendt, Stefan ^a,b   Heyns, Marc ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c INTEL CORPORATION   (United States)

Author keywords

Flatband voltage; Hafnium silicate; High ; Interface layer; Oxide charge; Slant etch SiO2; Thickness variation

Indexed keywords

FLATBAND VOLTAGE; HAFNIUM SILICATE; INTERFACE LAYER; OXIDE CHARGE; SLANT-ETCH SIO2; THICKNESS VARIATION;

DIELECTRIC MATERIALS; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM; HAFNIUM COMPOUNDS;

SILICATES;

EID: 33846425064     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.882412     Document Type: Article

References (11)

1. Y. Yasuda, N. Kimizuka, T. Iwamoto, S. Fujieda, T. Ogura, H. Watanabe, T. Tatsumi, I. Yamamoto, K. Ito, H. Watanabe, Y. Yamagata, and K. Imai, "A 65nm-node LSTP (low standby power) poly-Si/a-Si/HfSiON transistor with high ion-istandby ratio and reliability," in VLSI Symp. Tech. Dig., Jun. 2004, pp. 40-41.
2. T. Yamaguchi, R. Iijima, T. Ino, A. Nishiyama, H. Satake, and N. Fukushima, "Additional scattering effects for mobility degradation in Hf-silicate gate MISFETs," in IEDM Tech. Dig., Dec. 2002, pp. 621-624.
3. M. Houssa, M. Aoulaiche, S. Van Elshocht, S. De Gendt, G. Groeseneken, and M. M. Heyns, "Negative bias temperature instabilities in HfSiON/ TaN-based pMOSFETs," in IEDM Tech. Dig., Dec. 2004, pp. 121-124.
4. K. Torii, Y. Shimamoto, S. Saito, K. Obata, T. Yamauchi, and D. Hisamoto, "Fixed charge induced mobility degradation and its recovery in MISFETs with Al2O3 gate dielectric," in Proc. IWGI, Tokyo, Japan, Dec. 2001, vol. 8.5, p. 230.
5. R. Jha, J. Gurganos, Y. H. Kim, R. Choi, J. Lee, and V. Misra, "A capacitance-based methodology for work function extraction of metals on high-k," IEEE Electron Device Lett., vol. 25, no. 6, p. 420, Jun. 2004.
6. H. C. Wen, H. N. Alshareef, H. Luan, K. Choi, P. Lysaght, H. R. Harris, C. Huffman, G. A. Brown, G. Bersuker, P. Zeitzoff, H. Huff, P. Majhi, and B. H. Lee, "Systematic investigation of amorphous transition-metalsilicon-nitride electrodes for metal gate CMOS applications," in VLSI Symp. Tech. Dig., 2005, p. 46.
7. Y. T. Hou, F. Y. Yen, P. F. Hsu, V. S. Chang, P. S. Lim, C. L. Hung, L. G. Yao, J. C. Jiang, H. J. Lin, Y. Jin, S. M. Jang, H. J. Tao, S. C. Chen, and M. S. Liang, "High performance tantalum carbide metal gate stacks for nMOSFET application," in IEDM Tech. Dig., 2005, pp. 31-34.
8. 2/TaN and SiON/TaN nMOS transistors," Microelectron. Eng., vol. 45, no. 5/6, pp. 779-782, May Jun., 2005.
9. Y. Takahashi, S. Imaki, K. Ohnishi, and M. Yoshikawa, "Test structure for determining the charge distribution in oxide of MOS structure," in Proc. IEEE Int. Conf. Microelectron. Test Structures, Mar. 1995, vol. 8, p. 243.
10. 2-based/polycrystalline-Si gate stacks," Appl. Phys. Lett., vol. 83, no. 3, pp. 533-535, 2003.
11. 2 gate stacks," IEEE Electron Device Lett., vol. 26, no. 1, p. 20, Jan. 2005.