Soft-error charge-sharing mechanisms at sub-100nm technology nodes

Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2007, Pages 213-216

  Massengill, L W ^a   Amusan, O A ^a   Dasgupta, S ^a   Sternberg, A L ^a   Black, J D ^a   Witulski, A F ^a   Bhuva, B L ^a   Alles, M L ^a  

^a VANDERBILT UNIVERSITY   (United States)

Author keywords

Charge collection; Charge sharing; SER; SEU mechanisms; Single event effects; Soft errors

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; MECHANISMS; SENSITIVITY ANALYSIS;

CHARGE COLLECTIONS; CHARGE-SHARING; CMOS TECHNOLOGY NODE; INDUCED CHARGES; INTEGRATED CIRCUIT (IC) DESIGN; INTERNATIONAL CONFERENCES; SOFT ERRORS; SUB-100 NM; TECHNOLOGY NODES;

TECHNOLOGY;

EID: 47349105195     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2007.4299576     Document Type: Conference Paper

References (8)

1. The International Technology Roadmap for Semiconductors, 2005 edition.
2. B.D. Olson, D. Ball, K.M. Warren, L.W. Massengill, N. Haddad, S. Doyle, D. McMorrow, "Simultaneous SE Charge Sharing and Parasitic Bipolar Conduction in a Highly Scaled SRAM Design", IEEE Trans. on Nuclear Science, vol. 52, no. 6, December 2005.
3. J.D. Black, A.L. Sternberg, M.L. Alles, A.F. Witulski, B.L. Bhuva, L.W. Massengill, J.M. Benedetto, M.P. Baze, J.L. Wert, M.G. Hubert, "HBD Isolation Techniques for Multiple Node Charge Collection Mitigation", IEEE Trans. on Nuclear Science, vol. 52, no. 6, December 2005.
4. B.D. Olson, O.A. Amusan, S. Dasgupta, L.W. Massengill, A.F. Witulski, B.L. Bhuva, K.M. Warren, and D.R. Ball "Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Guard Contacts in 130 nm and 90 nm CMOS Technology", Proc. Intl. Radiation Effects on Components and Systems Conference, Athens, September, 2006.
5. O.A. Amusan, A.F. Witulski, L.W. Massengill, B.L. Bhuva, P.R. Fleming, M.L. Alles, A.L. Sternberg, J.D. Black, and R.D. Schrimpf, "Charge Collection and Charge Sharing in a 130 nm CMOS Technology", IEEE Trans. On Nuclear Science, vol. 53, no. 6, December 2006.
6. J. Maiz, S. Hareland, K. Zhang, P. Armstrong, "Characterization of multi-bit soft error events in advanced SRAMs", Intl. Electron Devices Meeting 2003 Technical Digest, Dec. 2003.
7. A.H. Johnston, R.E. Plaag, M.P. Baze, "The Effect of Circuit Topology on Radiation-Induced Latchup" IEEE Trans. on Nuclear Science, vol. 36, no. 6, December 1989.
8. E.L. Petersen, J.C. Pckel, E.C. Smith, P.J. Rudeck, J.R. Letaw, "Geometrical Factors in SEE Rate Calculations," IEEE Transactions on Nuclear Science, vol. 40, no. 6, December 1993.