Compact modeling of a Flash memory cell including substrate-bias-dependent hot-electron gate current

IEEE Transactions on Electron Devices

Volumn 51, Issue 10, 2004, Pages 1726-1730

  Sonoda, Ken'ichiro ^a   Tanizawa, Motoaki ^a   Shimizu, Satoshi ^a   Araki, Yasuhiro ^a   Kawai, Shinji ^a   Ogura, Taku ^a   Kobayashi, Shin'ichi ^a   Ishikawa, Kiyoshi ^a   Eimori, Takahisa ^a   Inoue, Yasuo ^a   Ohji, Yuzuru ^a   Kotani, Norihiko ^b  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b HIROSHIMA INTERNATIONAL UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC NETWORK SYNTHESIS; ELECTRON TUNNELING; ELECTRONS; EQUIVALENT CIRCUITS; HOT CARRIERS; MATHEMATICAL MODELS; OPTIMIZATION;

CHARGE INJECTION; ELECTRON INJECTION; EPROM; FLASH MEMORY CELL; FOWLER-NORDHEIM TUNNELING;

FLASH MEMORY;

EID: 5444253347     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.834915     Document Type: Article

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