Effects of parasitic capacitance, external resistance, and local stress on the RF performance of the transistors fabricated by standard 65-nm CMOS technologies

IEEE Transactions on Electron Devices

Volumn 55, Issue 10, 2008, Pages 2712-2717

  Kim, Han Su ^a   Kim, Jedon ^a   Chung, Chulho ^a   Lim, Jinsung ^a   Jeong, Joohyun ^a   Joe, Jin Hyoun ^a   Park, Jaehoon ^a   Park, Kang Wook ^a   Oh, Hansu ^a   Yoon, Jong Shik ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Effective gate width; Gate poly (GP) pitch; Layout effects; Radio frequency (RF) performance

Indexed keywords

CMOS INTEGRATED CIRCUITS; TRANSISTORS; WELDS;

EFFECTIVE GATE WIDTH; GATE POLY (GP) PITCH; LAYOUT EFFECTS; RADIO-FREQUENCY (RF) PERFORMANCE;

CAPACITANCE;

EID: 53649108382     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2003995     Document Type: Article

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