Gate layout and bonding pad structure of a RF n-MOSFET for low noise performance

IEEE Electron Device Letters

Volumn 21, Issue 12, 2000, Pages 607-609

  Kim, Cheon Soo ^a   Park, Jung Woo ^a   Yu, Hyun Kyu ^a   Cho, Hanjin ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; ELECTRIC GROUNDING; ELECTRIC RESISTANCE; GATES (TRANSISTOR); TECHNOLOGY TRANSFER;

GATE RESISTANCE; UNIT FINGER WIDTH;

MOSFET DEVICES;

EID: 0034499917     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.887481     Document Type: Article

References (11)

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