Geometry optimization of sub-100nm node RF CMOS utilizing three dimensional TCAD simulation

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn 2006-January, Issue , 2006, Pages 319-322

  Tatsumi, Takaaki ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ELECTRONIC DESIGN AUTOMATION; GEOMETRY;

90 NM TECHNOLOGY NODE; DEVICE SIMULATORS; GATE RESISTANCE; GEOMETRICAL FACTORS; GEOMETRICAL VARIATIONS; GEOMETRY OPTIMIZATION; HIGH FREQUENCY CHARACTERISTICS; OPTIMUM COMBINATION;

MOSFET DEVICES;

EID: 84957885796     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/essder.2006.307702     Document Type: Conference Paper

References (7)

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6. B.Razavi, et.al., "Impact of Distributed Gate Resistance on the Performance of MOS Devices", IEEE Trans. Circuits and Systems, Vol.41, No.11, pp.750-754, 1994.
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