Self-aligned double patterning gains NAND flash favor

Semiconductor International

Volumn 31, Issue 10, 2008, Pages 37-45

  Bencher, Chris ^a  

^a APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 52449121559     PISSN: 01633767     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (11)

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3. M. LaPedus, "Intel, Micron Roll 34-nm NAND Device," EE Times, May 29, 2008.
4. W.Y. Jung et al., "Patterning With Amorphous Carbon Spacer for Expanding the Resolution Limit of Current Lithography Tool," Proc. SPIE, March 27, 2007, Vol. 6520, p. 65201C.
5. H. Zhuang et al., "Patterning Strategies for Gate Level Tip-Tip Distance Reduction in SRAM Cell for 45nm and Beyond," Proc. Semiconductor Technology ISTC 2007, Vol. 2007-01, p. 154.
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8. M.C. Smayling, C. Bencher, H.D. Chen, H. Dai and M.P. Duane, "APF Pitch-Halving for 22nm Logic Cells Using Gridded Design Rules," Proc. SPIE, April 9. 2008, Vol. 6925, p. 69251E.
9. W.H. Arnold, "Toward 3nm Overlay and Critical Dimension Uniformity: An Integrated Error Budget for Double Patterning Lithography," Proc. SPIE March 20, 2008, Vol. 6924, p. 692404-1.
10. H. Mukai, E. Shiobara. S. Takahashi and K. Hashimoto, "A Study of CD Budget in Spacer Patterning Technology; Proc. SPIE, March 20, 2008, Vol. 6924, p. 692406-2.
11. C. Bencher, Y. Chen, H. Dai. W. Montgomery and L. Huli, "22nm Half-Pitch Patterning by CVD Spacer Self-Aligned Double Patterning," Proc. SPIE, March 20, 2008, Vol. 6924, p. 69244E.