Quick addition of decimals using reversible conservative logic

Proceedings of the 15th International Conference on Advanced Computing and Communications, ADCOM 2007

Volumn , Issue , 2007, Pages 191-196

  James, Rekha K ^a   Shahana, T K ^a   Jacob, K Poulose ^a   Sasi, Sreela ^b  

^a Department of Physics   (India)

^b GANNON UNIVERSITY   (United States)

Author keywords

Decimal arithmetic; Delay reduction; Fault detection; Reversible logic

Indexed keywords

COMPUTATION THEORY; DELAY CIRCUITS; FAULT DETECTION; LOGIC GATES; QUANTUM COMPUTERS;

CONSERVATIVE LOGIC; DECIMAL ARITHMETIC; DELAY REDUCTION; HIGH SPEED CIRCUIT; IMPLEMENTATION STRATEGIES; POWER OPTIMIZATION; QUANTUM COMPUTING; REVERSIBLE LOGIC;

COMPUTER CIRCUITS;

EID: 52249106400     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/adcom.2007.94     Document Type: Conference Paper

References (14)

1. R. Landauer, "Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research Development, 5, pp. 183 -191, 1961.
2. Bennett, C., "Logical Reversibility of Computation," IBM Journal of Research and Development, 17, pp.525-532, 1973.
3. T. Toffoli., "Reversible Computing", Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science, 1980.
4. Md. Hafiz Hasan Babu and A. R. Chowdhury, "Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-bit Parallel Adder", VLSI Design '05, pp.255-260, Jan 2005.
5. th International Conference on VLSI Design (VLSI Design 2006), pp. 387-392, Jan 2006.
6. B. Parhami; "Fault Tolerant Reversible Circuits" Proc. 40th Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, October 2006.
7. R. Feynman, "Quantum Mechanical Computers", Optical News, 1985, pp.11-20.
8. E. Fredkin and T. Toffoli, "Conservative logic", Intl. J. Theoretical Physics, Vol 21, 1982, pp. 219-253.
9. J.W. Bruce, M.A. Thornton, L. Shivakumariah, P.S. Kokate, X.Li, "Efficient Adder Circuits Based on a Conservative Logic Gate", Proceedings of the IEEE Computer Society Annual Symposium on VLSI, April 2002, PA, USA, pp 83-88.
10. H. Thapliyal and M.B Srinivas, "A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures", Tenth Asia-Pacific Computer Systems Architecture Conference, Singapore, Oct 24 -26, 2005.
11. Dmitri Maslov, "Reversible Logic Synthesis", PhD Dissertation, Computer Science Department, University of New Brunswick, Canada, October 2003.
12. A. Agrawal and N. K. Jha, "Synthesis of reversible logic," in Proc. Design Automation & Test in Europe Conf., Feb. 2004, pp. 21 384-21385.
13. P. Gupta, A. Agrawal, N. K. Jha, "An algorithm for synthesis of reversible logic circuits", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems", Nov. 2006, Volume: 25, Issue 11, pp. 2317-2330.
14. Guowu Yang; Fei Xie; Xiaoyu Song; Hung, W.N.N.; Perkowski, M.A., "A constructive Algorithm for Reversible Logic synthesis" IEEE Congress on Evolutionary Computation, July 2006, pp. 2416- 2421.