Temperature-based phase change memory model for pulsing scheme assessment

Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2008, Pages 199-202

  Liao, Yi Bo ^a   Lin, Jun Tin ^a   Chiang, Meng Hsueh ^a  

^a NATIONAL ILAN UNIVERSITY   (Taiwan)

Author keywords

Compact model; Phase change memory (PCM); SPICE; Verilog A

Indexed keywords

CIRCUIT SIMULATION; ELECTRIC CONDUCTIVITY; ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; PULSE CODE MODULATION; TECHNOLOGICAL FORECASTING; TECHNOLOGY;

CIRCUIT DESIGN TECHNIQUES; CIRCUIT SIMULATORS; COMPACT MODEL; COMPACT MODELING; INPUT CURRENTS; INTEGRATED CIRCUIT DESIGN; INTERNATIONAL CONFERENCES; MEMORY EFFECTS; PCM TECHNOLOGY; PHASE CHANGE MEMORY (PCM); PHASE-CHANGE MEMORIES; SPICE; TECHNOLOGY DEVELOPMENT; VERILOG-A;

PHASE CHANGE MEMORY;

EID: 51849168976     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2008.4567278     Document Type: Conference Paper

References (9)

1. G. Atwood and R. Bez, "Current status of Chalcogenide phase change memory," in Proc. Device Research Conference, 2005, vol. 1, pp. 29-33.
2. A. L. Lacaita, "Physics and performance of phase change memories," in Proc. Simulation of Semiconductor Processes and Devices, 2005, pp. 267-270.
3. D. Ielmini, A. L. Lacaita, A. Pirovano, F. Pellizzer, and R. Bez, "Analysis of phase distribution in phase-change nonvolatile memories," IEEE Electron Device Letters, vol. 25, pp. 507-509, Jul. 2004.
4. S. Ramaswamy, K. Hunt, D. Maimon, B. Li, A. Bumgarner, J. Rodgers, and L. Burcin, "Progress on design and demonstration of the 4Mb chalcogenide-based random access memory," in Proc. IEEE Symposium on Non-Volatile Memory Tech., Nov. 2004, pp. 137-142.
5. Y.-B. Liao, Y.-K. Chen, and M.-H. Chiang, "An analytical compact PCM model accounting for partial crystallization," in Proc. IEEE Electron Devices and Solid-State Circuit Conf., Dec. 2007, pp. 625-628.
6. X. Q. Wei et al., "Universal HSPICE model for chalcogenide based phase change memory elements," in Proc. IEEE Nonvolatile Memory Technology Symp., Nov. 2004, vol. 15-17, pp. 88-91.
7. X. Q. Wei, et al., "HSPICE macromodel of PCRAM for binary and multilevel storage," IEEE Trans. Electron Devices, vol. 53, pp. 56-62, Jan. 2006.
8. A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez, "Scaling analysis of phase-change memory technology," in IEDM Tech. Dig., Dec. 2003, pp. 29.6.1-29.6.4.
9. Y.-B. Liao, Y.-K. Chen, and M.-H. Chiang. "Phase change memory modeling using Verilog-A," in Proc. IEEE Behavioral Modeling and Simulation Conf., Sep. 2007, pp. 159-164.