-
1
-
-
84969804262
-
Digital Integrated Circuits : A design perspective
-
Second Edtion, Chapter 7. pp
-
J.M.Rabaey, "Digital Integrated Circuits : A design perspective," Second Edtion, Prentice Hall Electronics and VLSI Series, Chapter 7. pp. 354-356, 2003
-
(2003)
Prentice Hall Electronics and VLSI Series
, pp. 354-356
-
-
Rabaey, J.M.1
-
2
-
-
0033116422
-
Comparative Analysis of Master-Slave latches and Flip-Flops for High-Performance and Low-Power Systems
-
Apr
-
Vladimir Stojanovic and Vojin G. Oklobdzija, 'Comparative Analysis of Master-Slave latches and Flip-Flops for High-Performance and Low-Power Systems," IEEE Journal Solid-State Circuits, vol. 34, No. 4, pp. 536-548, Apr. 1999
-
(1999)
IEEE Journal Solid-State Circuits
, vol.34
, Issue.4
, pp. 536-548
-
-
Stojanovic, V.1
Oklobdzija, V.G.2
-
3
-
-
0030083355
-
Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements
-
Feb
-
H. Partovi, et al, "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements," IEEE International Solid-State Circuits Conference, pp. 138-139, Feb. 1996
-
(1996)
IEEE International Solid-State Circuits Conference
, pp. 138-139
-
-
Partovi, H.1
-
4
-
-
0032662594
-
A New Family of Semidynamic and Dynamic Flip-Flops with Embeded logic for High Performance Processors
-
May
-
F. Klass, et al, "A New Family of Semidynamic and Dynamic Flip-Flops with Embeded logic for High Performance Processors," IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 712-716, May 1999
-
(1999)
IEEE Journal of Solid-State Circuits
, vol.34
, Issue.4
, pp. 712-716
-
-
Klass, F.1
-
5
-
-
0342906692
-
Improved sense-amplifier based flip-flop: Design and measurements
-
Jun
-
B. Nikolic, et al., "Improved sense-amplifier based flip-flop: design and measurements," IEEE Journal of Solid-State circuits, vol. 35, pp. 876-884, Jun. 2000
-
(2000)
IEEE Journal of Solid-State circuits
, vol.35
, pp. 876-884
-
-
Nikolic, B.1
-
6
-
-
0035429510
-
Conditional-capture flip-flop for statistical power reduction
-
Aug
-
B. S. Kong, et al, "Conditional-capture flip-flop for statistical power reduction," IEEE Journal of Solid-State Circuits, vol. 36, pp. 1263-1271, Aug. 2001
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, pp. 1263-1271
-
-
Kong, B.S.1
-
9
-
-
0037969007
-
A Clock-Skew Absorbing Flip-Flop
-
Digest of Technical Papers. ISSCC, IEEE International, 2003
-
Nikola Nedovic, et al, "A Clock-Skew Absorbing Flip-Flop", Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, Vol. 1, pp. 342-497, 2003
-
(2003)
Solid-State Circuits Conference
, vol.1
, pp. 342-497
-
-
Nedovic, N.1
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