SCOPUS 정보 검색 플랫폼

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 120-127

SOI transistor model for fast transient simulation

(9) Nadezhin, D a Gavrilov, S b Glebov, A b Egorov, Y c Zolotov, V d Blaauw, D c Becer, M c Ardelea, A c Patel, A c

a MCST (Russian Federation)

b Microstyle (Russian Federation)

c MOTOROLA INC (United States)

d UNIVERSITY OF MICHIGAN (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; CONVERGENCE OF NUMERICAL METHODS; ERROR ANALYSIS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; MOSFET DEVICES; POLYNOMIAL APPROXIMATION; SWITCHING;

GATE VOLTAGE; GRID DISCRETIZATION;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0346148499 PISSN: 10923152 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/iccad.2003.159680 Document Type: Conference Paper

Times cited : (12)

References (10)

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- Lewis, D.M.¹

5
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- Levy, R.; Blaauw, D.; Braca, G.; Dasgupta, A.; Grinshpon, A.; Chanhee Oh; Orshav, B.; Sirichotiyakul, S.; Zolotov, V.,; "ClariNet: a noise analysis tool for deep submicron design", DAC 2000
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.