-
1
-
-
33847749484
-
A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs
-
Yoocheol Shin, Jungdal Choi, Changseok Kang, Changhyun Lee, Ki-Tae Park, Jang-Sik Lee, Jongsun Sel, Viena Kim, Byeongin Choi, Jaesung Sim, Dongchan Kim, Hag-ju Cho, and Kinam Kim, " A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs," Techn. Dig. of IEDM, 2005, pp.327-330.
-
(2005)
Techn. Dig. of IEDM
, pp. 327-330
-
-
Shin, Y.1
Choi, J.2
Kang, C.3
Lee, C.4
Park, K.-T.5
Lee, J.-S.6
Sel, J.7
Kim, V.8
Choi, B.9
Sim, J.10
Kim, D.11
Cho, H.-J.12
Kim, K.13
-
2
-
-
0141761571
-
Novel multi-bit SONOS type flash memory using a high-k charge trapping layer
-
T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, " Novel multi-bit SONOS type flash memory using a high-k charge trapping layer," in VLSI Symp. Tech. Dig., 2003, pp.27-28.
-
(2003)
VLSI Symp. Tech. Dig
, pp. 27-28
-
-
Sugizaki, T.1
Kobayashi, M.2
Ishidao, M.3
Minakata, H.4
Yamaguchi, M.5
Tamura, Y.6
Sugiyama, Y.7
Nakanishi, T.8
Tanaka, H.9
-
4
-
-
4344661847
-
-
Yan-Ny Tan, Wai-Kin Chim, Byung jin Cho, and Wee-Kiong Choi, Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer, IEEE Trans. Electron Devices, 51, no. 7, pp.1143-1147, 2004.
-
Yan-Ny Tan, Wai-Kin Chim, Byung jin Cho, and Wee-Kiong Choi, " Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer," IEEE Trans. Electron Devices, 51, no. 7, pp.1143-1147, 2004.
-
-
-
-
5
-
-
0028495167
-
Design and scaling of a SONOS multidielectirc device for nonvolatile memory applications
-
M.L. French, C.Y.Chen, H. Sathianathan, and M.H.White," Design and scaling of a SONOS multidielectirc device for nonvolatile memory applications," IEEE Trans. Compon., Packag., Manuf. Technol.A,17, no.3, pp..390-397, 1994.
-
(1994)
IEEE Trans. Compon., Packag., Manuf. Technol.A
, vol.17
, Issue.3
, pp. 390-397
-
-
French, M.L.1
Chen, C.Y.2
Sathianathan, H.3
White, M.H.4
-
6
-
-
0003610719
-
-
John Wiley & Sons, Inc, New-York NY, pp
-
E. H. Nicollian, and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, John Wiley & Sons, Inc., New-York NY, pp.495-508, 1982.
-
(1982)
MOS (Metal Oxide Semiconductor) Physics and Technology
, pp. 495-508
-
-
Nicollian, E.H.1
Brews, J.R.2
-
7
-
-
34250753325
-
Characterization of charge traps in Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) structures for embedded flash memories
-
Takeshi Ishida, Yutaka Okuyama, and Renichi Yamada, " Characterization of charge traps in Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) structures for embedded flash memories," in Proceedings of IRPS, 2006, pp. 516-522.
-
(2006)
Proceedings of IRPS
, pp. 516-522
-
-
Ishida, T.1
Okuyama, Y.2
Yamada, R.3
-
8
-
-
27344443406
-
2 high-dielectric-constant gate oxide
-
2 high-dielectric-constant gate oxide," Appl. Phys. Lett, 87, 183505, 2005.
-
(2005)
Appl. Phys. Lett
, vol.87
, pp. 183505
-
-
Xiong, K.1
Robertson, J.2
Gibson, M.C.3
Clark, S.J.4
-
9
-
-
48649084463
-
Anomalous Electron Storage Decrease in MONOS' Nitride Layers Thinner than 4nm
-
to be submitted
-
T. Ishida, T. Mine, D. Hisamoto, Y. Shimamoto, and R. Yamada, "Anomalous Electron Storage Decrease in MONOS' Nitride Layers Thinner than 4nm" IEEE Elec. Dev. Let., to be submitted,2008.
-
(2008)
IEEE Elec. Dev. Let
-
-
Ishida, T.1
Mine, T.2
Hisamoto, D.3
Shimamoto, Y.4
Yamada, R.5
-
10
-
-
0024985779
-
Charge Transport and Storage of Low Programming Voltage SONOS/MONOS Memory Devices
-
Fank R. Libsch, and Marvin H. White, "Charge Transport and Storage of Low Programming Voltage SONOS/MONOS Memory Devices", Solid-State Electronics, Vol. 33, pp. 105-126, 1990.
-
(1990)
Solid-State Electronics
, vol.33
, pp. 105-126
-
-
Libsch, F.R.1
White, M.H.2
-
11
-
-
0009735981
-
Electronic Processes in Silicon Nitride
-
Oct
-
S. Manzini, "Electronic Processes in Silicon Nitride", J. Appl. Phys., Vol. 62, pp. 3278-3284, Oct. 1987.
-
(1987)
J. Appl. Phys
, vol.62
, pp. 3278-3284
-
-
Manzini, S.1
-
12
-
-
4043048598
-
Charge decay characteristics of silicon-oxide-nitride-oxide- silicon structure at elevated temperatures and extraction of the nitride trap density distribution
-
Tae Hun Kim, Jae Sung Sim, Jong Duk Lee, Hyung Cheol Shin, and Byung-Gook Park, " Charge decay characteristics of silicon-oxide-nitride-oxide- silicon structure at elevated temperatures and extraction of the nitride trap density distribution," Appl. Phys. Lett,85, pp.660-662, 2004.
-
(2004)
Appl. Phys. Lett
, vol.85
, pp. 660-662
-
-
Hun Kim, T.1
Sung Sim, J.2
Duk Lee, J.3
Cheol Shin, H.4
Park, B.-G.5
|