MAPS: An integrated framework for MPSoC application parallelization

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 754-759

  Ceng, J ^a   Castrillon, J ^a   Sheng, W ^a   Scharwachter H ^a   Leupers, R ^a   Ascheid, G ^a   Meyr, H ^a   Isshiki, T ^b   Kunieda, H ^b  

^a RWTH AACHEN UNIVERSITY   (Germany)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Embedded; MPSoC programming; Parallelization; Software

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING; MAPS;

EMBEDDED; INTEGRATED FRAMEWORKS; MPSOC PROGRAMMING; PARALLELIZATION; SOFTWARE;

OPTICAL PROJECTORS;

EID: 51549106553     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555920     Document Type: Conference Paper

References (28)

1. The OpenMP Specification for Parallel Programming. http://www.openmp. org.
2. Standard for Information Technology - Portable Operating System Interface (POSIX). Shell and utilities. IEEE Std 1003.1-2004, The Open Group Base Specifications Issue 6, section 2.9. IEEE and The Open Group.
3. M. Kulkarni, K. Pingali, B. Walter, G. Ramanarayanan, K. Bala, and L. P. Chew. Optimistic Parallelism Requires Abstractions. SIGPLAN Not., 42(6):211-222, 2007.
4. L. Thiele, I. Bacivarov, W. Haid, and K. Huang. Mapping Applications to Tiled Multiprocessor Embedded Systems. In ACSD 07, pages 29-40, 2007.
5. T. Wiangtong, P. Cheung, and W. Luk. Hardware/Software Codesign: a Systematic Approach Targeting Data-intensive Applications. IEEE Signal Processing Magazine, 22(3):14-22, 2005.
6. M. I. Gordon, W. Thies, M. Karczmarek, J. Lin, A. S. Meli, A. A. Lamb, C. Leger, J. Wong, H. Hoffmann, D. Maze, and S. Amarasinghe. A Stream Compiler for Communication-Exposed Architectures. SIGOPS Oper. Syst. Rev., 36(5):291-303, 2002.
7. Embedded Software Stuck at C. http://www.eetimes.com/news/design/ showArticle.jhtml?articleID=202102427.
8. M. Z. Urfianto, T. Isshiki, A. U. Khan, D. Li, and H. Kunieda. A Multiprocessor System-on-Chip Architecture with Enhanced Compiler Support and Efficient Interconnect. In IP-SOC 2006, Design and Reuse, S.A., 2006.
9. M. Z. Urfianto, T. Isshiki, A. U. Khan, D. Li, and H. Kunieda. A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development. IEICE Trans. Fundamentals, Vol. E91-A, No. 4, Apr. 2008.
10. T. Isshiki, M. Z. Urfianto, A. U. Khan, D. Li, and H. Kunieda. Tightly-Coupled-Thread Model: A New Design Framework for Multiprocessor System-on-Chips. In Design Automation Symposium (Japan), 2006.
11. U. Banerjee, R. Eigenmann, A. Nicolau, and D. A. Padua. Automatic Program Parallelization. Proceedings of the IEEE, 81(2):211-243, 1993.
12. R. Leupers. Code Selection for Media processors with SIMD Instructions. In DATE '00, pages 4-8. ACM, 2000.
13. M. H. Hall, S. P. Amarasinghe, B. R. Murphy, S.-W. Liao, and M. S. Lam. Detecting Coarse-Grain Parallelism Using an Interprocedural Parallelizing Compiler. In Super-computing '95, page 49. ACM, 1995.
14. S. Verdoolaege, H. Nikolov, and T. Stefanov. Improved Derivation of Process Networks. In ODES-4, 2006.
15. T. Harriss, R. Walke, B. Kienhuis, and E. Deprettere. Compilation from Matlab to Process Networks Realized in FPGA. In Design Automation of Embedded Systems, volume 7, 2002.
16. I. Karkowski and H. Corporaal. Design of Heterogeneous Multi-Processor Embedded Systems: Applying Functional Pipelining. In PACT '97, page 156. 1997.
17. R. N. Weng and T. Wolf. Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures. In in Proc. of Third Workshop on Network Processors and Applications (NP-3), pages 103-119, Feb. 2004.
18. G. Ottoni, R. Rangan, A. Stoler, and D. I. August. Automatic Thread Extraction with Decoupled Software Pipelining. In MICRO 38, pages 105-118. IEEE Computer Society, 2005.
19. W. Thies, V. Chandrasekhar, and S. Amarasinghe. A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs. In MICRO-40, 2007.
20. M. J. Bridges, N. Vachharajani, Y. Zhang, T. Jablin, and D. I. August. Revisiting the Sequential Programming Model for Multi-Core. In MICRO-40, 2007.
21. Eclipse C/C++ Development Tooling. http://www.eclipse.org/cdt.
22. R. Leupers, O. Wahlen, M. Hohenauer, T. Kogel, and P. Marwedel. An Executable Intermediate Representation for Retargetable Compilation and High-Level Code Optimization. In SAMOS, 2003.
23. M. Hind. Pointer Analysis: Haven't We Solved This Problem Yet? In PASTE '01, pages 54-61. ACM Press, 2001.
24. T. Kempf, K. Karuri, S. Wallentowitz, G. Ascheid, R. Leupers, and H. Meyr. A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation. In DATE '06, pages 468-473, 2006.
25. A. V. Aho, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley Longman Publishing Co., Inc., 1986.
26. M. Ester, H.-P. Kriegel, J. Sander, and X. Xu. A Density-Based Algorithm for Discovering Clusters in Large Spatial Databases with Noise. In KDD 96, pages 468-473, Aug. 1996.
27. Independent JPEG Group. http://www.ijg.org/.
28. DSPStone. http://www.ert.rwthaachen.de/Projekte/Tools/DSPSTONE/ dspstone.html.