A multiprocessor SoC architecture with efficient communication infrastructure and advanced compiler support for easy application development

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E91-A, Issue 4, 2008, Pages 1185-1196

  Zalfany Urfianto, Mohammad ^a   Isshiki, Tsuyoshi ^a   Ullah Khan, Arif ^a   Li, Dongju ^a   Kunieda, Hiroaki ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Crossbar interconnect; Multiprocessor on a chip; System on chips; VLSI

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER ARCHITECTURE; MULTIPROCESSING SYSTEMS; PROGRAM COMPILERS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS; TIMING JITTER;

APPLICATION DEVELOPMENT; COMMUNICATION MODULES; CROSSBAR INTERCONNECT; EFFICIENT COMMUNICATIONS; MULTIPROCESSOR ARRAYS; MULTIPROCESSOR SYSTEM ON CHIPS; MULTIPROCESSOR-ON-A-CHIP; VLSI;

INTEGRATED CIRCUIT DESIGN;

EID: 51549090271     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e91-a.4.1185     Document Type: Conference Paper

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