Predictive runtime verification of multi-processor SoCs in SystemC

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 948-953

  Sen, Alper ^a   Ogale, Vinit ^b   Abadir, Magdy S ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Assertion; Deadlock; ESL; Predictive verification; SystemC

Indexed keywords

ASSERTION; DEADLOCK; ESL; PREDICTIVE VERIFICATION; SYSTEMC;

AUTOMATION; CHANNEL CAPACITY; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ERRORS; MULTIPROCESSING SYSTEMS; SYSTEMS ANALYSIS;

LOGIC DESIGN;

EID: 51549104734     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555956     Document Type: Conference Paper

References (15)

1. R. Agarwal and S. D. Stoller. Run-Time Detection of Potential Deadlocks for Programs with Locks, Semaphores, and Condition Variables. In Proceedings of the Workshop on Parallel and Distributed Systems: Testing and Debugging (PADTAD), 2006.
2. E. Cheung, P. Satapathy, V. Pham, H. Hsieh, and X. Chen. Runtime Deadlock Analysis of SystemC Designs. In Proceedings of the IEEE International High-Level Design Validation and Test Workshop (HLDVT), 2006.
3. W. Ecker, V. Esen, T. Steininger, M. Velten, and M. Hull. Implementation of a Transaction Level Assertion Framework in SystemC. In Proceedings of the Conference on Design Automation and Test in Europe (DATE), 2007.
4. C. Fidge. Logical Time in Distributed Computing Systems. IEEE Computer, 24(8):28-33, Aug. 1991.
5. D. Grosse and R. Drechsler. Formal verification of LTL formulas for SystemC designs. In Proceedings of the International Symposium on Circuits and Systems (ISCAS), 2003.
6. A. Habibi and S. Tahar. On the extension of SystemC by System Verilog assertions. In Proceedings of Canadian Conference on Electrical and Computer Engineering, 2004.
7. C. Helmstetter, F. Maraninchi, L. Maillet-Contoz, and M. Moy. Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip. In Proceedings of the International Conference on Formal Methods in Computer Aided Design (FMCAD), 2006.
8. A. Kasuya and T. Tesfaye. Verification methodologies in a TLM-to-RTL design flow. In Proceedings of the Design Automation Conference (DAC), 2007.
9. L. Lamport. Time, Clocks, and the Ordering of Events in a Distributed System. Communications of the ACM (CACM), 21(7):558-565, July 1978.
10. F. Mattern. Virtual Time and Global States of Distributed Systems. In Parallel and Distributed Algorithms: Proceedings of the Workshop on Distributed Algorithms (WDAG), 1989.
11. M. Moy, F. Maraninchi, and L. Maillet-Contoz. LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level. In Int'l Conference on Application of Concurrency to System Design, 2005.
12. Open SystemC Initiative, http://www.systemc.org/.
13. A. Sen and V. K. Garg. Formal Verification of Simulation Traces Using Computation Slicing. IEEE Transactions on Computers, 56(4):511-527, Apr. 2007.
14. K. Sen, G. Rosu, and G. Agha. Runtime Safety Analysis of Multithreaded Programs. In Proceedings of the Symposium on the Foundations of Software Engineering (FSE), 2003.
15. M. Y. Vardi. Formal Techniques for SystemC Verification; Position Paper. In Proceedings of the Design Automation Conference (DAC), 2007.