Implementation of a transaction level assertion framework in systemC

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 894-899

  Ecker, Wolfgang ^a   Esen, Volkan ^b   Steininger, Thomas ^b   Velten, Michael ^b   Hull, Michael ^c  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

^c UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROBLEM SOLVING; QUALITY ASSURANCE;

ABSTRACTION LEVELS; HARDWARE DESIGN; TRANSACTION LEVEL (TL); VERIFICATION METHODOLOGIES;

SYSTEMS ANALYSIS;

EID: 34548316927     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364406     Document Type: Conference Paper

References (13)

1. Accellera. Open Verification Library. http://www.accellera.org/ activities/ovl/.
2. X. Chen, Y. Luo, H. Hsieh, L. Bhuyan, and F. Balarin. Assertion Based Verification and Analysis of Network Processor Architectures. Design Automation for Embedded Systems, 2004.
3. W. Ecker, V. Esen, M. Hull, T. Steininger, and M. Veiten. A Prototypic Language for Transaction Level Assertions. In Design and Verification Conference (DVCon), February 2007.
4. D. Große and R. Drechsler. Formal Verification of LTL Formulas For SystemC Designs. In International Symposium on Circuits and Systems, volume 5, pages 245-248, May 2003.
5. A. Habibi and S. Tahar. Assertion and Model Checking of SystemC. In North American SystemC Users Group Meeting, San Diego, California, USA, June 2004.
6. A. Habibi and S. Tahar. On the extension of SystemC by SystemVerilog Assertions. In Canadian Conference on Electrical & Computer Engineering, volume 4, pages 1869-1872, Niagara Falls, Ontario, Canada, May 2004.
7. A. Habibi and S. Tahar. Towards an Efficient Assertion Based Verification of SystemC Designs. In In Proc. of the High Level Design Validation and Test Workshop, pages 19-22, Sonoma Valley, California, USA, November 2004.
8. IEEE Computer Society. SystemVerilog LRM P1800. http://www.ieee.org.
9. Mentor Graphics. Advanced Verification Methodology Cookbook. Mentor Graphics, http://www.mentor.com. 2006.
10. B. Niemann and C. Haubelt. Assertion Based Verification of Transaction Level Models. In ITG/GI/GMM Workshop, volume 9, pages 232-236, Dresden, Germany, February 2006.
11. T. Peng and B. Baruah. Using Assertion-based Verification Classes with SystemC Verification Library. Synopsys Users Group, Boston, 2003.
12. P. Peranandam, R. Weiss, J. Ruf., and T. Kropf. Transactional Level Verification and Coverage Metrics by Means of Symbolic Simulation. In ITG/GI/GMM Workshop, February 2004.
13. R. J. Weiss, J. Ruf, T. Kropf, and W. Rosenstiel. Efficient and Customizable Integration of Temporal Properties into SystemC. Lausanne, Switzerland, September 2005.