On the extension of systemC by SystemVerilog assertions

Canadian Conference on Electrical and Computer Engineering

Volumn 4, Issue , 2004, Pages 1869-1872

  Habibi, Ali ^a   Tahar, Sofiene ^a  

^a Civil and Environmental Engineering   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ASSERTION BASED VERIFICATION (ABV); SYSTEM LEVEL LANGUAGES (SLL); SYSTEM-ON-A-CHIP; SYSTEMVERILOG ASSERTIONS;

CHIP SCALE PACKAGES; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SOFTWARE; OBJECT ORIENTED PROGRAMMING; SEMANTICS;

C (PROGRAMMING LANGUAGE);

EID: 4944240463     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2004.1347573     Document Type: Conference Paper

References (10)

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4. I. Beer, S. Ben-David, C. Eisner, D. Fisman, A. Gringauze and Y. Rodeh. &The temporal logic sugar&. In Computer-Aided Verification, volume 2102 of Lecture Notes in Computer Science, pp. 363-367, Springer-Verlag, 2001.
5. B. Bentley. Validating the Intel Pentium 4 Microprocessor. In Proc. of the 38th Design Automation Conference, pp. 244-248, 2001.
6. M. Kantrowitz and L. Noack. &I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DEC-chip21164 Alpha Microprocessor&. In Proc. ACM/IEEE Design Automation Conference, 1996.
7. Open SystemC Initiative. SystemC 2.0.1 language reference manual. Open SystemC Initiative, pp. 428, 2003.
8. P. R. Panda. SystemC: a modeling platform supporting multiple design abstractions. In In Proc. of the 14th International Symposium on Systems synthesis, pp. 75-80, 2001.
9. SystemC: http://www.systemc.org, 2004.
10. VHDL-200X (The Future of VHDL): http://www.eda.org/vhdl-200x, 2004.