Formal verification of simulation traces using computation slicing

IEEE Transactions on Computers

Volumn 56, Issue 4, 2007, Pages 511-527

  Sen, Alper ^a   Garg, Vijay K ^b  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

Formal verification; Lattice theory; Partial order; Runtime verification; Simulation; Temporal logic

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL EFFICIENCY; COMPUTER SIMULATION; TEMPORAL LOGIC;

COMPUTATION SLICING; FORMAL VERIFICATION; LATTICE THEORY; PARTIAL ORDER TRACE MODEL; RUNTIME VERIFICATION; SIMULATION TRACES;

VERIFICATION;

EID: 34047193962     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.1011     Document Type: Article

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