Type-matching clock tree for zero skew clock gating

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 714-719

  Chang, Chia Ming ^a   Huang, Shih Hsu ^a   Ho, Yuan Kai ^a   Lin, Jia Zong ^a   Wang, Hsin Po ^b   Lu, Yu Sheng ^b  

^a CHUNG YUAN CHRISTIAN UNIVERSITY   (Taiwan)

^b SpringSoft Inc   (Taiwan)

Author keywords

Clock network synthesis; Gated clock; Physical design

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CLOCKS; INDUSTRIAL ENGINEERING; LOGIC GATES; MICROPROCESSOR CHIPS; TELECOMMUNICATION NETWORKS;

CLOCK NETWORK SYNTHESIS; CLOCK TREE; GATED CLOCK; PHYSICAL DESIGN;

CLOCKS;

EID: 51549085883     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555912     Document Type: Conference Paper

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