Process flow and manufacturing concept for embedded active devices

Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004

Volumn , Issue , 2004, Pages 605-609

  Aschenbrenner, R ^a   Ostmann, A ^a   Neumann, A ^b   Reich, H ^b  

^a FRAUNHOFER IZM   (Germany)

^b TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; MICROELECTRONICS; PRINTED CIRCUIT BOARDS; THICKNESS MEASUREMENT;

CHIP IN POLYMER (CIP); DESIGN CYCLES; EMBEDDED ACTIVE DEVICES; PROCESS FLOW;

ELECTRONICS PACKAGING;

EID: 28444498414     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. R. Aschenbrenner and H. Reichl, "Micro Joining Technology Trend of Electronic Devices in Europe" Int. Welding Symposium, Invited Lecture, November 20-22, 2001, Kobe, Japan
2. A. Ostmann, A. Neumann, S. Weser, E. Jung, L. Böttcher and H. Reichl, "Realization of a Stackable Package Using Chip in Polymer Technology", Polytronic Conference, June 23.-26. 2002, Zalaegerszeg, Hungary
3. Project Website http://www.hidingdies.net.
4. J.-C. Sanchez "Wafer thinning and stress release", Proc. Workshop on Ultra-thin Silicon Packaging at Fraunhofer ISIT, September 26 2002, Itzehoe, Germany.
5. E. Jung, A. Neumann, D. Wojakowski, A. Ostmann, C. Landesberger, R. Aschenbrenner and H. Reichl, "Ultra Thin Chips for Miniaturized Products", ECTC 2002, San Diego.
6. Ch. Scheiring, "Automated bonding of ultra-thin dice", Proc. Workshop on Ultra-thin Silicon Packaging at Fraunhofer ISIT, September 26 2002, Itzehoe, Germany.
7. Borland, W.J. and Ferguson S., "Embedded Passive Components in Printed Wiring Boards: A Technology Review," CircuiTree, March 2001.
8. Robert T. Croswell, Ph.D. et al., "Embedded Mezzanine Technology for Printed Wiring Boards." IPC Printed Circuits Expo 2002, March 2002.