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Volumn , Issue , 2007, Pages 67-70

A 480-MHz to 1-GHz sub-picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13-μm CMOS

Author keywords

[No Author keywords available]

Indexed keywords

ACOUSTIC FIELDS; CALIBRATION; ELECTRIC CLOCKS; TUNING; VARIABLE FREQUENCY OSCILLATORS;

EID: 51349127672     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425733     Document Type: Conference Paper
Times cited : (23)

References (8)
  • 1
    • 0036858568 scopus 로고    scopus 로고
    • A Low-Power Small-Area 7.28-ps-Jitter 1-GHz DLL-Based Clock Generator
    • Nov
    • C. Kim, I.-C. Hwang, and S.-M. Kang, "A Low-Power Small-Area 7.28-ps-Jitter 1-GHz DLL-Based Clock Generator," IEEE J. Solid-State Circuits, vol. 37, pp. 1414-1420, Nov. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , pp. 1414-1420
    • Kim, C.1    Hwang, I.-C.2    Kang, S.-M.3
  • 2
    • 0242551728 scopus 로고    scopus 로고
    • Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL
    • Nov
    • J. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, "Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL," IEEE J. Solid-State Circuits, vol. 38, pp. 1795-1803, Nov. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , pp. 1795-1803
    • Maneatis, J.1    Kim, J.2    McClatchie, I.3    Maxey, J.4    Shankaradas, M.5
  • 3
    • 0038494025 scopus 로고    scopus 로고
    • A Subpicosecond Jitter PLL for Clock Generation in 0.12-μm CMOS
    • Jul
    • N. D. Dalt and C. Sander, "A Subpicosecond Jitter PLL for Clock Generation in 0.12-μm CMOS," IEEE J. Solid-State Circuits, vol. 38, pp. 1275-1278, Jul. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , pp. 1275-1278
    • Dalt, N.D.1    Sander, C.2
  • 4
    • 22544465884 scopus 로고    scopus 로고
    • A Compact Triple-Band Low-Jitter Digital LC PLL With Programmable Coil in 130-nm CMOS
    • Jul
    • N. D. Dalt, E. Edwin, P. Gregorius, and L. Gazsi, "A Compact Triple-Band Low-Jitter Digital LC PLL With Programmable Coil in 130-nm CMOS," IEEE J. Solid-State Circuits, vol. 40, pp. 1482-1490, Jul. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , pp. 1482-1490
    • Dalt, N.D.1    Edwin, E.2    Gregorius, P.3    Gazsi, L.4
  • 5
    • 15944397012 scopus 로고    scopus 로고
    • Minimum Achievable Phase Noise of RC Oscillators
    • Mar
    • R. Navid, T. Lee, and R. W. Dutton, "Minimum Achievable Phase Noise of RC Oscillators," IEEE J. Solid-State Circuits, vol. 40, pp. 630-637, Mar. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , pp. 630-637
    • Navid, R.1    Lee, T.2    Dutton, R.W.3
  • 6
    • 3042822147 scopus 로고    scopus 로고
    • A Δ-Σ Fractional-N Frequency Synthesizer Using a Wide-Band Integrated VCO and a Fast AFC Technique for GSM/GPRS/WCDMA Applications
    • Jul
    • H.-I. Lee, J.-K. Cho, K.-S. Lee, I.-C. Hwang, T.-W. Ahn, K.-S. Nah, and B.-H. Park, "A Δ-Σ Fractional-N Frequency Synthesizer Using a Wide-Band Integrated VCO and a Fast AFC Technique for GSM/GPRS/WCDMA Applications," IEEE J. Solid-State Circuits, vol. 39, pp. 340-349, Jul. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , pp. 340-349
    • Lee, H.-I.1    Cho, J.-K.2    Lee, K.-S.3    Hwang, I.-C.4    Ahn, T.-W.5    Nah, K.-S.6    Park, B.-H.7
  • 7
    • 33847730295 scopus 로고    scopus 로고
    • An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL
    • Feb
    • T.-H. Lin and Y.-J. Lai, "An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL," IEEE J. Solid-State Circuits, vol. 42, pp. 340-349, Feb. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , pp. 340-349
    • Lin, T.-H.1    Lai, Y.-J.2
  • 8
    • 0036641460 scopus 로고    scopus 로고
    • Fully Integrated 2.4-GHz LC-VCO Frequency Synthesizer With 3-ps Jitter in 0.18-μm Standard Digital CMOS Copper Technology
    • Jul
    • N. D. Dalt, S. Derksen, P. Greco, C. Sandner, H.schmid, and K. Strohmayer, "Fully Integrated 2.4-GHz LC-VCO Frequency Synthesizer With 3-ps Jitter in 0.18-μm Standard Digital CMOS Copper Technology," IEEE J. Solid-State Circuits, vol. 37, pp. 959-962, Jul. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , pp. 959-962
    • Dalt, N.D.1    Derksen, S.2    Greco, P.3    Sandner, C.4    schmid, H.5    Strohmayer, K.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.