A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 7, 2002, Pages 959-962

  Da Dalt, Nicola ^a,b   Derksen, Sven ^b   Greco, Patrizia ^b   Sandner, Christoph ^a,b   Schmid, Harald ^b   Strohmayer, Klaus ^b  

^a IEEE   (Austria)

^b INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

Digital PLL; Fractional divider; Frequency synthesizer; Jitter; LC VCO; Phase noise; PLL

Indexed keywords

FRACTIONAL DIVIDERS;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; JITTER; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

FREQUENCY SYNTHESIZERS;

EID: 0036641460     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.1015697     Document Type: Article

References (8)

1. A differentially tuned 1.73-GHz-1.99-GHz quadrature CMOS VCO for DECT, DCS1800 and GSM900 with a phase noise over tuning range between - 128 dBc/Hz and - 137 dBc/Hz at 600 kHz offset
2. A fully integrated analog front end macro for cable modem applications in 0.18-μm CMOS
3. A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching
4. High-speed CMOS circuit technique
5. A novel structure for DCO PLLs with equivalent 16-bit digital phase quantization, digital loop filter and 18-ps long-term jitter
6. Measurements and analysis of PLL jitter caused by digital switching noise
7. A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM wireless receivers