A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 7, 2003, Pages 1275-1278

  Da Dalt, Nicola ^a   Sandner, Christoph ^a  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

Clock generation; Frequency synthesizer; Jitter; LC VCO; Phase noise; Phase locked loop (PLL); Wideband PLL

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; ELECTRIC POTENTIAL; FREQUENCY SYNTHESIZERS; JITTER; SPURIOUS SIGNAL NOISE;

CLOCK GENERATION;

PHASE LOCKED LOOPS;

EID: 0038494025     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.813287     Document Type: Article

References (6)

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