Implementing synchronous models on loosely time triggered architectures

IEEE Transactions on Computers

Volumn 57, Issue 10, 2008, Pages 1300-1314

  Tripakis, Stavros ^a   Pinello, Claudio ^a   Benveniste, Albert ^b   Sangiovanni Vincent, Alberto ^c   Caspi, Paul ^d   Di Natale, Marco ^e  

^a CADENCE DESIGN SYSTEMS   (United States)

^b CAMPUS DE BEAULIEU   (France)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d VERIMAG   (France)

^e SCUOLA SUPERIORE SANT ANNA   (Italy)

Author keywords

Code generation; Distributed systems; Embedded systems; Loosely time triggered architecture; Semantics preserving implementation; Synchronous models

Indexed keywords

COMPUTER NETWORKS; SPECIFICATIONS;

CODE GENERATION; DISTRIBUTED SYSTEMS; EMBEDDED SYSTEMS; LOOSELY TIME-TRIGGERED ARCHITECTURE; SEMANTICS-PRESERVING IMPLEMENTATION; SYNCHRONOUS MODELS;

INFORMATION THEORY;

EID: 51349124945     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2008.81     Document Type: Article

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