A protocol for loosely time-triggered architectures

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2491, Issue , 2002, Pages 252-265

  Benveniste, Albert ^a   Caspi, Paul ^b   Guernic, Paul Le ^a   Marchand, Hervè ^a   Talpin, Jean Pierre ^a   Tripakis, Stavros ^b  

^a CAMPUS DE BEAULIEU   (France)

^b VERIMAG   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTER ARCHITECTURE; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SOFTWARE; MODEL CHECKING; REAL TIME CONTROL;

COHERENT SYSTEM; LOGICAL CLOCK; MODEL CHECKER; PHYSICAL SYSTEMS; SYNCHRONOUS DESIGNS; SYNCHRONOUS LANGUAGES; TIME TRIGGERED; TIME-TRIGGERED ARCHITECTURES;

NETWORK ARCHITECTURE;

EID: 84948979164     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45828-x_19     Document Type: Conference Paper

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