Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip

Discrete Applied Mathematics

Volumn 123, Issue 1-3, 2002, Pages 103-127

  Albrecht, Christoph ^a   Korte, Bernhard ^a   Schietke, Jürgen ^a   Vygen, Jens ^a  

^a UNIVERSITY OF BONN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84867939579     PISSN: 0166218X     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0166-218X(01)00339-0     Document Type: Article

References (22)

1. U. Bünnagel, Effiziente Implementierung von Netzwerkalgorithmen, Diploma Thesis, University of Bonn, 1998 (in German).
2. R.B. Deokar, S. Sapatnekar, A graph-theoretic approach to clock skew optimization, Proceedings of the IEEE International Symposium on Circuits and Systems, 1994, pp. 407-410.
3. G. Doettling, K.J. Getzlaff, B. Leppla, W. Lipponer, T. Pflueger, T. Schlipf, D. Schmunkamp, and U. Wille S/390 parallel enterprise server generation3: a balanced system and cache structure IBM J. Res. Dev. 41 1997 405 428
4. J.P. Fishburn Clock skew optimization Trans. Comput. C-39 1990 945 951
5. J.H. Huang, A.B. Kahng, C.-W.A. Tsao, On bounded-skew routing tree problem, Proceedings of the 32nd Design Automation Conference, 1995, pp. 508-513.
6. R.M. Karp A characterization of the minimum mean cycle in a digraph Discrete Math. 23 1978 309 311
7. B. Kick, U. Baur, J. Koehl, T. Ludwig, and T. Pflueger Standard-cell-based design methodology for high performance support chips IBM J. Res. Dev. 41 1997 505 514
8. J. Koehl, U. Baur, T. Ludwig, B. Kick, T. Pflueger, A flat, timing-driven design system for a high-performance CMOS processor chipset, Proceedings of the Conference "Design, Automation and Test in Europe", 1998, pp. 312-320.
9. J. Lee, D.T. Tang, and C.K. Wang A timing analysis algorithm for circuits with level-sensitive latches IEEE Trans. Comput.-Aided Des. Integrated Circuits Systems 15 1996 535 543
10. I. Lin, J.A. Ludwig, K. Eng, Analyzing cycle stealing on synchronous circuits with level-sensitive latches, Proceedings of the 29th ACM/IEEE Design Automation Conference, 1992, pp. 393-398.
11. N. Megiddo Applying parallel computation algorithms in the design of serial algorithms J. Assoc. Comput. Machinery 30 1983 852 865
12. K. Muuss, Clockskew Optimierung, Diploma Thesis, University of Bonn, 1994 (in German).
13. J.L. Neves, E.G. Friedman, Optimal clock skew scheduling tolerant to process, variations, Proceedings of the 33rd Design Automation Conference, 1996, pp. 623-628.
14. c: timing verification and optimal clocking of synchronous digital circuits, Proceedings of the IEEE International Conference on Computer-Aided Design, 1990, pp. 552-555.
15. J. Schietke, Timing-Optimierung beim physikalischen Layout von nicht-hierarchischen Designs hochintegrierter Logikchips, Ph.D. Thesis, University of Bonn, 1999 (in German).
16. H. Schneider, and M.H. Schneider Towers and cycle covers for max-balanced graph Math. Oper. Res. 16 1991 208 222
17. N. Shenoy, R.K. Brayton, Graph algorithms for clock schedule optimization, Proceedings of the IEEE International Conference on Computer-Aided Design, 1992, pp. 132-136.
18. T.G. Szymanski, Computing optimal clock schedules, Proceedings of the 29th ACM/IEEE Design Automation Conference, 1992, pp. 399-404.
19. T.G. Szymanski, N. Shenoy, Verifying clock schedules, Proceedings of the IEEE International Conference on Computer-Aided Design, 1992, pp. 124-131.
20. R.-S. Tsay Exact zero skew IEEE Trans. Comput.-Aided Des. 21 1991 205 221
21. J. Vygen, Plazierung im VLSI-Design und ein zweidimensionales Zerlegungsproblem, Ph.D. Thesis, University of Bonn, 1996 (in German).
22. N.E. Young, R.E. Tarjan, and J.B. Orlin Faster parametric shortest path and minimum balance algorithms Networks 21 1991 205 221