A robust digital delay line architecture in a 0.13μm CMOS technology node for reduced design and process sensitivities

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 148-153

  Raha, P ^a   Randall, S ^a   Jennings, R ^a   Helmick, B ^a   Amerasekera, A ^a   Haroun, B ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Clocks; CMOS process; CMOS technology; Delay lines; Digital signal processing; Frequency synchronization; Frequency synthesizers; Process design; Robustness; Silicon

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRIC DELAY LINES; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUIT DESIGN; PROCESS DESIGN; ROBUSTNESS (CONTROL SYSTEMS); SENSITIVITY ANALYSIS; SIGNAL PROCESSING; SILICON;

CMOS PROCESSS; CMOS TECHNOLOGY; DIGITAL DELAY LINES; FREQUENCY SYNCHRONIZATION; HIGH OPERATING FREQUENCY; MOBILE APPLICATIONS; PHASE SYNCHRONIZATION; TARGET SPECIFICATIONS;

DESIGN;

EID: 11144297886     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996719     Document Type: Conference Paper

References (3)

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2. R. Fried, "Low-Power Digital PLL with One Cycle Frequency Lock-In Time for Clock Synthesis up to 100MHz using 32,768Hz Reference Clock", IEEE ASIC Conf. Proceedings, pp. 291-294, 1996.
3. K. Minami, e.a., "A 1GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges", ISSCC Dig. Tech. Papers, pp. 350-351, Feb. 2000.