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Volumn , Issue , 2007, Pages 45-50

Leakage current reduction in data caches on embedded systems

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER PROGRAMMING LANGUAGES; DATA REDUCTION; ENERGY CONSERVATION; ENERGY POLICY; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; STANDARDS;

EID: 50249084490     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPC.2007.95     Document Type: Conference Paper
Times cited : (9)

References (19)
  • 3
    • 50249152863 scopus 로고    scopus 로고
    • Semiconductor Industry Association
    • Semiconductor Industry Association. The International Technology Roadmap for Semiconductors (ITRS), 2003. http://public.itrs.net/Files/2003ITRS/ Home2003.htm.
    • (2003)
  • 6
    • 50249126552 scopus 로고    scopus 로고
    • Processors
    • Intel Pentium D 920 and Pentium D 930 Processors. http://www.intel. com/products/processor/pentium d/.
    • Intel Pentium D 920 and Pentium D , vol.930
  • 15
    • 84948961559 scopus 로고    scopus 로고
    • th International Symposium on Microarchitecture
    • November
    • th International Symposium on Microarchitecture, November 2002.
    • (2002)
    • Yang, J.1    Gupta, R.2
  • 16
    • 25844484595 scopus 로고    scopus 로고
    • Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories
    • July
    • Y. J. Chang and F. Lai. Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories. IEEE Micro, 25(4):20-32, July 2005.
    • (2005) IEEE Micro , vol.25 , Issue.4 , pp. 20-32
    • Chang, Y.J.1    Lai, F.2
  • 17
    • 4644295620 scopus 로고    scopus 로고
    • st International Symposium on Computer Architecture, June 2004.
    • st International Symposium on Computer Architecture, June 2004.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.