Compiler techniques for reducing data cache miss rate on a multithreaded architecture

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4917 LNCS, Issue , 2008, Pages 353-368

  Sarkar, Subhradyuti ^a   Tullsen, Dean M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MISS RATES; CACHE-CONSCIOUS; COMPILER TECHNIQUES; CONFLICT MISSES; DATA CACHING; DATA LAYOUTS; DATA OBJECTS; EMBEDDED ARCHITECTURES; INTERNATIONAL CONFERENCES; MULTI-THREADING; MULTITHREADED ARCHITECTURES; WORKING SET;

ARCHITECTURE; CONSERVATION; EFFICIENCY; ENERGY EFFICIENCY; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; MICROPROCESSOR CHIPS; MULTITASKING;

PROGRAM COMPILERS;

EID: 49949100101     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-77560-7_24     Document Type: Conference Paper

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