Dynamic capacity-speed tradeoffs in SMT processor caches

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4367 LNCS, Issue , 2007, Pages 136-150

  López, Sonia ^a   Dropsho, Steve ^b   Albonesi, David H ^c   Garnica, Oscar ^a   Lanchares, Juan ^a  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^b EPFL   (Switzerland)

^c Department of Obstetrics Gynecology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; PROBLEM SOLVING; SYSTEMS ANALYSIS;

GLOBALLY ASYNCHRONOUS; MULTI-THREADED SUPPORT; PROCESSOR CACHES; SIMULTANEOUS MULTI-THREADED (SMT);

MICROPROCESSOR CHIPS;

EID: 38149043351     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-69338-3_10     Document Type: Conference Paper

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