Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 4, 2006, Pages 805-813

  Nomura, Masahiro ^a,c,d   Ikenaga, Yoshifumi ^a,d   Takeda, Koichi ^a,d   Nakazawa, Yoetsu ^a   Aimoto, Yoshiharu ^b,d   Hagihara, Yasuhiko ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c IEEE   (Japan)

^d Institute of Electronics   (Japan)

Author keywords

CMOS; Leakage current; Low power; Monitor; Switching current; V TH control; V DD control

Indexed keywords

LOW POWER; SWITCHING CURRENT; V TH CONTROL; V DD CONTROL;

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MONITORING; OPTIMIZATION; POWER CONTROL; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

ELECTRIC POWER MEASUREMENT;

EID: 33645698251     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870796     Document Type: Conference Paper

References (7)

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